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authorVictor Gallardo <vgallardo@apm.com>2010-10-08 14:25:27 +0400
committerJosh Boyer <jwboyer@linux.vnet.ibm.com>2010-11-29 18:05:06 +0300
commitd164f6d4f9108126f69ba2963cf6fb7ef4ba9232 (patch)
tree9f0f97180ee4f7486974c657588e8ee65074fcc2 /Documentation/powerpc
parent46f5221049bb46b0188aad6b6dfab5dbc778be22 (diff)
downloadlinux-d164f6d4f9108126f69ba2963cf6fb7ef4ba9232.tar.xz
powerpc/4xx: Add suspend and idle support
Add suspend/resume support for 4xx compatible CPUs. See /sys/power/state for available power states configured in. Add two different idle states (idle-wait and idle-doze) controlled via sysfs. Default is idle-wait. cat /sys/devices/system/cpu/cpu0/idle [wait] doze To save additional power, use idle-doze. echo doze > /sys/devices/system/cpu/cpu0/idle cat /sys/devices/system/cpu/cpu0/idle wait [doze] Signed-off-by: Victor Gallardo <vgallardo@apm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'Documentation/powerpc')
-rw-r--r--Documentation/powerpc/dts-bindings/4xx/cpm.txt52
1 files changed, 52 insertions, 0 deletions
diff --git a/Documentation/powerpc/dts-bindings/4xx/cpm.txt b/Documentation/powerpc/dts-bindings/4xx/cpm.txt
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+PPC4xx Clock Power Management (CPM) node
+
+Required properties:
+ - compatible : compatible list, currently only "ibm,cpm"
+ - dcr-access-method : "native"
+ - dcr-reg : < DCR register range >
+
+Optional properties:
+ - er-offset : All 4xx SoCs with a CPM controller have
+ one of two different order for the CPM
+ registers. Some have the CPM registers
+ in the following order (ER,FR,SR). The
+ others have them in the following order
+ (SR,ER,FR). For the second case set
+ er-offset = <1>.
+ - unused-units : specifier consist of one cell. For each
+ bit in the cell, the corresponding bit
+ in CPM will be set to turn off unused
+ devices.
+ - idle-doze : specifier consist of one cell. For each
+ bit in the cell, the corresponding bit
+ in CPM will be set to turn off unused
+ devices. This is usually just CPM[CPU].
+ - standby : specifier consist of one cell. For each
+ bit in the cell, the corresponding bit
+ in CPM will be set on standby and
+ restored on resume.
+ - suspend : specifier consist of one cell. For each
+ bit in the cell, the corresponding bit
+ in CPM will be set on suspend (mem) and
+ restored on resume. Note, for standby
+ and suspend the corresponding bits can
+ be different or the same. Usually for
+ standby only class 2 and 3 units are set.
+ However, the interface does not care.
+ If they are the same, the additional
+ power saving will be seeing if support
+ is available to put the DDR in self
+ refresh mode and any additional power
+ saving techniques for the specific SoC.
+
+Example:
+ CPM0: cpm {
+ compatible = "ibm,cpm";
+ dcr-access-method = "native";
+ dcr-reg = <0x160 0x003>;
+ er-offset = <0>;
+ unused-units = <0x00000100>;
+ idle-doze = <0x02000000>;
+ standby = <0xfeff0000>;
+ suspend = <0xfeff791d>;
+};