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| author | Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2020-06-15 09:50:22 +0300 |
|---|---|---|
| committer | Jonathan Corbet <corbet@lwn.net> | 2020-06-19 23:10:13 +0300 |
| commit | 781885fdf09f55ff14172749258f7380f859f2ba (patch) | |
| tree | 7483ad342215ce587933882bdc2b6c2aefc2f394 /Documentation/sh/register-banks.rst | |
| parent | 7539b417626e5d5db132859678284e690771c499 (diff) | |
| download | linux-781885fdf09f55ff14172749258f7380f859f2ba.tar.xz | |
docs: sh: convert register-banks.txt to ReST
- Add a SPDX header;
- Adjust document title to follow ReST style;
- Add blank lines to make ReST markup happy
- Add it to sh/index.rst.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Link: https://lore.kernel.org/r/adf117cf1edd7f43cb839ff2800f4315dfbcce13.1592203650.git.mchehab+huawei@kernel.org
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Diffstat (limited to 'Documentation/sh/register-banks.rst')
| -rw-r--r-- | Documentation/sh/register-banks.rst | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/Documentation/sh/register-banks.rst b/Documentation/sh/register-banks.rst new file mode 100644 index 000000000000..2bef5c8fcbbc --- /dev/null +++ b/Documentation/sh/register-banks.rst @@ -0,0 +1,40 @@ +.. SPDX-License-Identifier: GPL-2.0 + +========================================== +Notes on register bank usage in the kernel +========================================== + +Introduction +------------ + +The SH-3 and SH-4 CPU families traditionally include a single partial register +bank (selected by SR.RB, only r0 ... r7 are banked), whereas other families +may have more full-featured banking or simply no such capabilities at all. + +SR.RB banking +------------- + +In the case of this type of banking, banked registers are mapped directly to +r0 ... r7 if SR.RB is set to the bank we are interested in, otherwise ldc/stc +can still be used to reference the banked registers (as r0_bank ... r7_bank) +when in the context of another bank. The developer must keep the SR.RB value +in mind when writing code that utilizes these banked registers, for obvious +reasons. Userspace is also not able to poke at the bank1 values, so these can +be used rather effectively as scratch registers by the kernel. + +Presently the kernel uses several of these registers. + + - r0_bank, r1_bank (referenced as k0 and k1, used for scratch + registers when doing exception handling). + + - r2_bank (used to track the EXPEVT/INTEVT code) + + - Used by do_IRQ() and friends for doing irq mapping based off + of the interrupt exception vector jump table offset + + - r6_bank (global interrupt mask) + + - The SR.IMASK interrupt handler makes use of this to set the + interrupt priority level (used by local_irq_enable()) + + - r7_bank (current) |