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authorColin Ian King <colin.king@canonical.com>2020-10-22 17:26:53 +0300
committerJonathan Corbet <corbet@lwn.net>2020-10-23 01:11:04 +0300
commit94ebdd28fcab7ef1484cd98f4a8e8426fe207994 (patch)
tree49553999c4c115a66a959c70c44fc80a83ee7c48 /Documentation/vm/mmu_notifier.rst
parent030f066f677f297033772dcdce9538b968fbeb14 (diff)
downloadlinux-94ebdd28fcab7ef1484cd98f4a8e8426fe207994.tar.xz
docs/vm: trivial fixes to several spelling mistakes
Fix several spelling mistakes in vm documentation. Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20201022142653.254429-1-colin.king@canonical.com Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Diffstat (limited to 'Documentation/vm/mmu_notifier.rst')
-rw-r--r--Documentation/vm/mmu_notifier.rst2
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/vm/mmu_notifier.rst b/Documentation/vm/mmu_notifier.rst
index 47baa1cf28c5..df5d7777fc6b 100644
--- a/Documentation/vm/mmu_notifier.rst
+++ b/Documentation/vm/mmu_notifier.rst
@@ -89,7 +89,7 @@ they are write protected for COW (other case of B apply too).
So here because at time N+2 the clear page table entry was not pair with a
notification to invalidate the secondary TLB, the device see the new value for
-addrB before seing the new value for addrA. This break total memory ordering
+addrB before seeing the new value for addrA. This break total memory ordering
for the device.
When changing a pte to write protect or to point to a new write protected page