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authorRussell King <rmk+kernel@arm.linux.org.uk>2015-09-03 17:28:50 +0300
committerRussell King <rmk+kernel@arm.linux.org.uk>2015-09-03 17:28:50 +0300
commit3ff32a0def6e0d2e21a6c5ad1b00726592774018 (patch)
treeaf683b2cb62f7e5ee18cb109d15dcfd43769b984 /Documentation
parent40d3f02851577da27b5cbb1538888301245ef1e7 (diff)
parent81497953e37bc28209d9a647171ea93b4a99fc57 (diff)
downloadlinux-3ff32a0def6e0d2e21a6c5ad1b00726592774018.tar.xz
Merge branch 'devel-stable' into for-linus
Conflicts: drivers/perf/arm_pmu.c
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/arm/pmu.txt12
1 files changed, 9 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt
index 3b5f5d1088c6..435251fa9ce0 100644
--- a/Documentation/devicetree/bindings/arm/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/pmu.txt
@@ -26,13 +26,19 @@ Required properties:
Optional properties:
-- interrupt-affinity : Valid only when using SPIs, specifies a list of phandles
- to CPU nodes corresponding directly to the affinity of
+- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU
+ nodes corresponding directly to the affinity of
the SPIs listed in the interrupts property.
- This property should be present when there is more than
+ When using a PPI, specifies a list of phandles to CPU
+ nodes corresponding to the set of CPUs which have
+ a PMU of this type signalling the PPI listed in the
+ interrupts property.
+
+ This property should be present when there is more than
a single SPI.
+
- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
events.