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authorLinus Torvalds <torvalds@linux-foundation.org>2013-07-11 01:46:40 +0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-07-11 01:46:40 +0400
commit6664565681a1c0c95607ae2e30070352d9a563d0 (patch)
treefdd60bf602e1c26e87ab25ffd2cc370e0ab51eac /Documentation
parent496fd15bee6f2fd673ab992e5211c5f3c5bd6779 (diff)
parent01ce784acfa69a171afe6ec3f85a959546f2d18a (diff)
downloadlinux-6664565681a1c0c95607ae2e30070352d9a563d0.tar.xz
Merge tag 'iommu-updates-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull IOMMU updates from Joerg Roedel: "A few updates this time, most important and exiciting (to me) is: - The new ARM SMMU driver. This is a common IOMMU driver that will hopefully be used in a lot of upcoming ARM chips. So the mess in the past where every SOC had its own IOMMU will be over. Besides that: - Some important fixes in the IOMMU unmap path. There are fixes in the common code and also in the AMD IOMMU driver. - Other random fixes" * tag 'iommu-updates-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: MAINTAINERS: add entry for ARM system MMU driver iommu/arm: Add support for ARM Ltd. System MMU architecture documentation/iommu: Add description of ARM System MMU binding iommu: Use %pa and %zx instead of casting iommu/amd: Only unmap large pages from the first pte iommu: Fix compiler warning on pr_debug iommu/amd: Fix memory leak in free_pagetable iommu: Split iommu_unmaps iommu/{vt-d,amd}: Remove multifunction assumption around grouping iommu/omap: fix checkpatch warnings in omap iommu code iommu/omap: fix printk formats for dma_addr_t iommu/vt-d: DMAR reporting table needs at least one DRHD iommu/vt-d: Downgrade the warning if enabling irq remapping fails
Diffstat (limited to 'Documentation')
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+* ARM System MMU Architecture Implementation
+
+ARM SoCs may contain an implementation of the ARM System Memory
+Management Unit Architecture, which can be used to provide 1 or 2 stages
+of address translation to bus masters external to the CPU.
+
+The SMMU may also raise interrupts in response to various fault
+conditions.
+
+** System MMU required properties:
+
+- compatible : Should be one of:
+
+ "arm,smmu-v1"
+ "arm,smmu-v2"
+ "arm,mmu-400"
+ "arm,mmu-500"
+
+ depending on the particular implementation and/or the
+ version of the architecture implemented.
+
+- reg : Base address and size of the SMMU.
+
+- #global-interrupts : The number of global interrupts exposed by the
+ device.
+
+- interrupts : Interrupt list, with the first #global-irqs entries
+ corresponding to the global interrupts and any
+ following entries corresponding to context interrupts,
+ specified in order of their indexing by the SMMU.
+
+ For SMMUv2 implementations, there must be exactly one
+ interrupt per context bank. In the case of a single,
+ combined interrupt, it must be listed multiple times.
+
+- mmu-masters : A list of phandles to device nodes representing bus
+ masters for which the SMMU can provide a translation
+ and their corresponding StreamIDs (see example below).
+ Each device node linked from this list must have a
+ "#stream-id-cells" property, indicating the number of
+ StreamIDs associated with it.
+
+** System MMU optional properties:
+
+- smmu-parent : When multiple SMMUs are chained together, this
+ property can be used to provide a phandle to the
+ parent SMMU (that is the next SMMU on the path going
+ from the mmu-masters towards memory) node for this
+ SMMU.
+
+Example:
+
+ smmu {
+ compatible = "arm,smmu-v1";
+ reg = <0xba5e0000 0x10000>;
+ #global-interrupts = <2>;
+ interrupts = <0 32 4>,
+ <0 33 4>,
+ <0 34 4>, /* This is the first context interrupt */
+ <0 35 4>,
+ <0 36 4>,
+ <0 37 4>;
+
+ /*
+ * Two DMA controllers, the first with two StreamIDs (0xd01d
+ * and 0xd01e) and the second with only one (0xd11c).
+ */
+ mmu-masters = <&dma0 0xd01d 0xd01e>,
+ <&dma1 0xd11c>;
+ };