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| author | Johan Hovold <johan+linaro@kernel.org> | 2022-10-17 09:50:13 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-12-31 15:32:46 +0300 |
| commit | 0d0382b9c0d526fc643dc24a212a360b6ee19071 (patch) | |
| tree | 1a2559e51942cdf34253de540c739db62a71887a /Documentation | |
| parent | cd1e1735aeab49abc679218a79ee764c0d394880 (diff) | |
| download | linux-0d0382b9c0d526fc643dc24a212a360b6ee19071.tar.xz | |
phy: qcom-qmp-pcie: drop bogus register update
[ Upstream commit 2d93887cb4bac0a36ce9e146956f631ab7994680 ]
Since commit 0d58280cf1e6 ("phy: Update PHY power control sequence") the
PHY is powered on before configuring the registers and only the MSM8996
PCIe PHY, which includes the POWER_DOWN_CONTROL register in its PCS
initialisation table, may possibly require a second update afterwards.
To make things worse, the POWER_DOWN_CONTROL register lies at a
different offset on more recent SoCs so that the second update, which
still used a hard-coded offset, would write to an unrelated register
(e.g. a revision-id register on SC8280XP).
As the MSM8996 PCIe PHY is now handled by a separate driver, simply drop
the bogus register update.
Fixes: e4d8b05ad5f9 ("phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB") added support
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> #RB3
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20221017065013.19647-12-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions