diff options
author | Arnd Bergmann <arnd@arndb.de> | 2023-12-21 18:44:11 +0300 |
---|---|---|
committer | Arnd Bergmann <arnd@arndb.de> | 2023-12-21 18:45:21 +0300 |
commit | 76955bc85b50eb32ad841256206d9025945aa7e0 (patch) | |
tree | 65b2e81cc210926727925b0fb4f13c23aa7d36ab /Documentation | |
parent | 9bc75fe58d69cb1c7496cd9cb74b59e931c1e45b (diff) | |
parent | 5dc289e08a4d0704583d8df70181cbeb47c817d9 (diff) | |
download | linux-76955bc85b50eb32ad841256206d9025945aa7e0.tar.xz |
Merge tag 'mtk-dts64-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
MediaTek ARM64 DeviceTree updates for v6.8
This adds devicetree bindings and nodes for:
- Media Data Path 3 (MDP3) bindings and enablement on MT8195
- Smart Voltage Scaling (SVS) on MT8195
- LVTS SoC thermal on MT8192
- MT8188 SoC along with its resets, display bindings, and more
- MT8183 hardware video decoder (mtk-vcodec-dec)
Adds the following new machines:
- MT8188 Evaluation Board (EVB)
- MT8183 Chromebooks: Kukui-Katsu, Jacuzzi-Makomo, Pico, Pico6
Performs cleanups for various MediaTek SoCs and PMICs, and also
includes some spare fixes.
* tag 'mtk-dts64-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: (60 commits)
arm64: dts: mediatek: mt8192: Add Smart Voltage Scaling node
arm64: dts: mediatek: mt8195: Add SVS node and reduce LVTS_AP iospace
arm64: dts: mediatek: mt8183: Change iospaces for thermal and svs
arm64: dts: mediatek: mt8186: fix address warning for ADSP mailboxes
arm64: dts: mediatek: mt8186: Fix alias prefix for ovl_2l0
arm64: dts: mt6358: Drop bogus "regulator-fixed" compatible properties
arm64: dts: mt8183: kukui-jacuzzi: Drop bogus anx7625 panel_flag property
arm64: dts: Add MediaTek MT8188 dts and evaluation board and Makefile
dt-bindings: soc: mediatek: pwrap: Modify compatible for MT8188
dt-bindings: arm: mediatek: Add mt8188 pericfg compatible
dt-bindings: arm: Add compatible for MediaTek MT8188
arm64: dts: mediatek: mt8195: add DSI and MIPI DPHY nodes
dt-bindings: display: mediatek: dsi: add compatible for MediaTek MT8195
arm64: dts: mediatek: mt6358: Merge ldo_vcn33_* regulators
dt-bindings: arm: mediatek: convert audsys and mt2701-afe-pcm to yaml
arm64: dts: mediatek: mt8195: add MDP3 nodes
arm64: dts: mediatek: mt8195: revise VDOSYS RDMA node name
arm64: dts: mediatek: mt8183: correct MDP3 DMA-related nodes
dt-bindings: display: mediatek: padding: add compatible for MT8195
dt-bindings: display: mediatek: split: add compatible for MT8195
...
Link: https://lore.kernel.org/r/20231212114515.121695-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'Documentation')
29 files changed, 948 insertions, 356 deletions
diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index a5999b3afc35..6f2f64ae76fc 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -176,6 +176,10 @@ properties: - const: mediatek,mt8186 - items: - enum: + - mediatek,mt8188-evb + - const: mediatek,mt8188 + - items: + - enum: - mediatek,mt8192-evb - const: mediatek,mt8192 - items: @@ -235,6 +239,13 @@ properties: items: - const: google,kappa - const: mediatek,mt8183 + - description: Google Katsu (ASUS Chromebook Detachable CZ1) + items: + - enum: + - google,katsu-sku32 + - google,katsu-sku38 + - const: google,katsu + - const: mediatek,mt8183 - description: Google Kodama (Lenovo 10e Chromebook Tablet) items: - enum: @@ -244,6 +255,20 @@ properties: - google,kodama-sku32 - const: google,kodama - const: mediatek,mt8183 + - description: Google Makomo (Lenovo 100e Chromebook 2nd Gen MTK 2) + items: + - enum: + - google,makomo-sku0 + - google,makomo-sku1 + - const: google,makomo + - const: mediatek,mt8183 + - description: Google Pico (Acer Chromebook Spin 311) + items: + - enum: + - google,pico-sku1 + - google,pico-sku2 + - const: google,pico + - const: mediatek,mt8183 - description: Google Willow (Acer Chromebook 311 C722/C722T) items: - enum: diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt deleted file mode 100644 index 699776be1dd3..000000000000 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +++ /dev/null @@ -1,39 +0,0 @@ -MediaTek AUDSYS controller -============================ - -The MediaTek AUDSYS controller provides various clocks to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-audsys", "syscon" - - "mediatek,mt6765-audsys", "syscon" - - "mediatek,mt6779-audio", "syscon" - - "mediatek,mt7622-audsys", "syscon" - - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon" - - "mediatek,mt8167-audiosys", "syscon" - - "mediatek,mt8183-audiosys", "syscon" - - "mediatek,mt8192-audsys", "syscon" - - "mediatek,mt8516-audsys", "syscon" -- #clock-cells: Must be 1 - -The AUDSYS controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. - -Required sub-nodes: -------- -For common binding part and usage, refer to -../sonud/mt2701-afe-pcm.txt. - -Example: - - audsys: clock-controller@11220000 { - compatible = "mediatek,mt7622-audsys", "syscon"; - reg = <0 0x11220000 0 0x2000>; - #clock-cells = <1>; - - afe: audio-controller { - ... - }; - }; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml new file mode 100644 index 000000000000..45d4a6620041 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,audsys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek AUDSYS controller + +maintainers: + - Eugen Hristev <eugen.hristev@collabora.com> + +description: + The MediaTek AUDSYS controller provides various clocks to the system. + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt2701-audsys + - mediatek,mt6765-audsys + - mediatek,mt6779-audsys + - mediatek,mt7622-audsys + - mediatek,mt8167-audsys + - mediatek,mt8173-audsys + - mediatek,mt8183-audsys + - mediatek,mt8186-audsys + - mediatek,mt8192-audsys + - mediatek,mt8516-audsys + - const: syscon + - items: + # Special case for mt7623 for backward compatibility + - const: mediatek,mt7623-audsys + - const: mediatek,mt2701-audsys + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + audio-controller: + $ref: /schemas/sound/mediatek,mt2701-audio.yaml# + type: object + +required: + - compatible + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/mt2701-power.h> + #include <dt-bindings/clock/mt2701-clk.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + audsys: clock-controller@11220000 { + compatible = "mediatek,mt7622-audsys", "syscon"; + reg = <0 0x11220000 0 0x2000>; + #clock-cells = <1>; + + afe: audio-controller { + compatible = "mediatek,mt2701-audio"; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "afe", "asys"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; + + clocks = <&infracfg CLK_INFRA_AUDIO>, + <&topckgen CLK_TOP_AUD_MUX1_SEL>, + <&topckgen CLK_TOP_AUD_MUX2_SEL>, + <&topckgen CLK_TOP_AUD_48K_TIMING>, + <&topckgen CLK_TOP_AUD_44K_TIMING>, + <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, + <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, + <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, + <&topckgen CLK_TOP_AUD_I2S1_MCLK>, + <&topckgen CLK_TOP_AUD_I2S2_MCLK>, + <&topckgen CLK_TOP_AUD_I2S3_MCLK>, + <&topckgen CLK_TOP_AUD_I2S4_MCLK>, + <&audsys CLK_AUD_I2SO1>, + <&audsys CLK_AUD_I2SO2>, + <&audsys CLK_AUD_I2SO3>, + <&audsys CLK_AUD_I2SO4>, + <&audsys CLK_AUD_I2SIN1>, + <&audsys CLK_AUD_I2SIN2>, + <&audsys CLK_AUD_I2SIN3>, + <&audsys CLK_AUD_I2SIN4>, + <&audsys CLK_AUD_ASRCO1>, + <&audsys CLK_AUD_ASRCO2>, + <&audsys CLK_AUD_ASRCO3>, + <&audsys CLK_AUD_ASRCO4>, + <&audsys CLK_AUD_AFE>, + <&audsys CLK_AUD_AFE_CONN>, + <&audsys CLK_AUD_A1SYS>, + <&audsys CLK_AUD_A2SYS>, + <&audsys CLK_AUD_AFE_MRGIF>; + + clock-names = "infra_sys_audio_clk", + "top_audio_mux1_sel", + "top_audio_mux2_sel", + "top_audio_a1sys_hp", + "top_audio_a2sys_hp", + "i2s0_src_sel", + "i2s1_src_sel", + "i2s2_src_sel", + "i2s3_src_sel", + "i2s0_src_div", + "i2s1_src_div", + "i2s2_src_div", + "i2s3_src_div", + "i2s0_mclk_en", + "i2s1_mclk_en", + "i2s2_mclk_en", + "i2s3_mclk_en", + "i2so0_hop_ck", + "i2so1_hop_ck", + "i2so2_hop_ck", + "i2so3_hop_ck", + "i2si0_hop_ck", + "i2si1_hop_ck", + "i2si2_hop_ck", + "i2si3_hop_ck", + "asrc0_out_ck", + "asrc1_out_ck", + "asrc2_out_ck", + "asrc3_out_ck", + "audio_afe_pd", + "audio_afe_conn_pd", + "audio_a1sys_pd", + "audio_a2sys_pd", + "audio_mrgif_pd"; + + assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, + <&topckgen CLK_TOP_AUD_MUX2_SEL>, + <&topckgen CLK_TOP_AUD_MUX1_DIV>, + <&topckgen CLK_TOP_AUD_MUX2_DIV>; + assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, + <&topckgen CLK_TOP_AUD2PLL_90M>; + assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index 536f5a5ebd24..b3c6888c1457 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -32,6 +32,9 @@ properties: - mediatek,mt8183-mmsys - mediatek,mt8186-mmsys - mediatek,mt8188-vdosys0 + - mediatek,mt8188-vdosys1 + - mediatek,mt8188-vppsys0 + - mediatek,mt8188-vppsys1 - mediatek,mt8192-mmsys - mediatek,mt8195-vdosys1 - mediatek,mt8195-vppsys0 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml index 26158d0d72f3..33c94c491828 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml @@ -28,6 +28,7 @@ properties: - mediatek,mt8173-pericfg - mediatek,mt8183-pericfg - mediatek,mt8186-pericfg + - mediatek,mt8188-pericfg - mediatek,mt8195-pericfg - mediatek,mt8516-pericfg - const: syscon diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml index d7214d97b2ba..860570320545 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml @@ -43,8 +43,6 @@ properties: - mediatek,mt8188-vdecsys - mediatek,mt8188-vdecsys-soc - mediatek,mt8188-vencsys - - mediatek,mt8188-vppsys0 - - mediatek,mt8188-vppsys1 - mediatek,mt8188-wpesys - mediatek,mt8188-wpesys-vpp0 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml index 7fd42c8fdc32..b4c28e96dd55 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -24,6 +24,7 @@ properties: - enum: - mediatek,mt8173-disp-aal - mediatek,mt8183-disp-aal + - mediatek,mt8195-mdp3-aal - items: - enum: - mediatek,mt2712-disp-aal diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml index f21e44092043..b886ca0d89ea 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml @@ -26,6 +26,7 @@ properties: - mediatek,mt2701-disp-color - mediatek,mt8167-disp-color - mediatek,mt8173-disp-color + - mediatek,mt8195-mdp3-color - items: - enum: - mediatek,mt7623-disp-color diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml index 537e5304b730..4a7a9ff21996 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml @@ -35,6 +35,10 @@ properties: - enum: - mediatek,mt6795-dsi - const: mediatek,mt8173-dsi + - items: + - enum: + - mediatek,mt8195-dsi + - const: mediatek,mt8183-dsi reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml index 801fa66ae615..677882348ede 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml @@ -23,7 +23,11 @@ description: properties: compatible: - const: mediatek,mt8195-disp-ethdr + oneOf: + - const: mediatek,mt8195-disp-ethdr + - items: + - const: mediatek,mt8188-disp-ethdr + - const: mediatek,mt8195-disp-ethdr reg: maxItems: 7 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml deleted file mode 100644 index dd12e2ff685c..000000000000 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml +++ /dev/null @@ -1,88 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: MediaTek MDP RDMA - -maintainers: - - Chun-Kuang Hu <chunkuang.hu@kernel.org> - - Philipp Zabel <p.zabel@pengutronix.de> - -description: - The MediaTek MDP RDMA stands for Read Direct Memory Access. - It provides real time data to the back-end panel driver, such as DSI, - DPI and DP_INTF. - It contains one line buffer to store the sufficient pixel data. - RDMA device node must be siblings to the central MMSYS_CONFIG node. - For a description of the MMSYS_CONFIG binding, see - Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details. - -properties: - compatible: - const: mediatek,mt8195-vdo1-rdma - - reg: - maxItems: 1 - - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - clocks: - items: - - description: RDMA Clock - - iommus: - maxItems: 1 - - mediatek,gce-client-reg: - description: - The register of display function block to be set by gce. There are 4 arguments, - such as gce node, subsys id, offset and register size. The subsys id that is - mapping to the register of display function blocks is defined in the gce header - include/dt-bindings/gce/<chip>-gce.h of each chips. - $ref: /schemas/types.yaml#/definitions/phandle-array - items: - items: - - description: phandle of GCE - - description: GCE subsys id - - description: register offset - - description: register size - maxItems: 1 - -required: - - compatible - - reg - - power-domains - - clocks - - iommus - - mediatek,gce-client-reg - -additionalProperties: false - -examples: - - | - #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/clock/mt8195-clk.h> - #include <dt-bindings/power/mt8195-power.h> - #include <dt-bindings/gce/mt8195-gce.h> - #include <dt-bindings/memory/mt8195-memory-port.h> - - soc { - #address-cells = <2>; - #size-cells = <2>; - - rdma@1c104000 { - compatible = "mediatek,mt8195-vdo1-rdma"; - reg = <0 0x1c104000 0 0x1000>; - interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; - power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; - iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; - mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; - }; - }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml index eead5cb8636e..dae839279950 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml @@ -24,9 +24,13 @@ properties: - enum: - mediatek,mt8173-disp-merge - mediatek,mt8195-disp-merge + - mediatek,mt8195-mdp3-merge - items: - const: mediatek,mt6795-disp-merge - const: mediatek,mt8173-disp-merge + - items: + - const: mediatek,mt8188-disp-merge + - const: mediatek,mt8195-disp-merge reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml index 3e1069b00b56..c471a181d125 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml @@ -26,6 +26,7 @@ properties: - mediatek,mt8173-disp-ovl - mediatek,mt8183-disp-ovl - mediatek,mt8192-disp-ovl + - mediatek,mt8195-mdp3-ovl - items: - enum: - mediatek,mt7623-disp-ovl diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml new file mode 100644 index 000000000000..be07bbdc54e3 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,padding.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Display Padding + +maintainers: + - Chun-Kuang Hu <chunkuang.hu@kernel.org> + - Philipp Zabel <p.zabel@pengutronix.de> + +description: + Padding provides ability to add pixels to width and height of a layer with + specified colors. Due to hardware design, Mixer in VDOSYS1 requires + width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled, + we need Padding to deal with odd width. + Please notice that even if the Padding is in bypass mode, settings in + register must be cleared to 0, or undefined behaviors could happen. + +properties: + compatible: + enum: + - mediatek,mt8188-disp-padding + - mediatek,mt8195-mdp3-padding + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + items: + - description: Padding's clocks + + mediatek,gce-client-reg: + description: + GCE (Global Command Engine) is a multi-core micro processor that helps + its clients to execute commands without interrupting CPU. This property + describes GCE client's information that is composed by 4 fields. + 1. Phandle of the GCE (there may be several GCE processors) + 2. Sub-system ID defined in the dt-binding like a user ID + (Please refer to include/dt-bindings/gce/<chip>-gce.h) + 3. Offset from base address of the subsys you are at + 4. Size of the register the client needs + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: Phandle of the GCE + - description: Subsys ID defined in the dt-binding + - description: Offset from base address of the subsys + - description: Size of register + maxItems: 1 + +required: + - compatible + - reg + - power-domains + - clocks + - mediatek,gce-client-reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/mediatek,mt8188-clk.h> + #include <dt-bindings/power/mediatek,mt8188-power.h> + #include <dt-bindings/gce/mt8195-gce.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + padding0: padding@1c11d000 { + compatible = "mediatek,mt8188-disp-padding"; + reg = <0 0x1c11d000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_PADDING0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>; + }; + }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml index a8a5c9608598..e4affc854f3d 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml @@ -23,6 +23,7 @@ properties: oneOf: - enum: - mediatek,mt8173-disp-split + - mediatek,mt8195-mdp3-split - items: - const: mediatek,mt6795-disp-split - const: mediatek,mt8173-disp-split @@ -38,6 +39,21 @@ properties: the power controller specified by phandle. See Documentation/devicetree/bindings/power/power-domain.yaml for details. + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4 arguments, + such as gce node, subsys id, offset and register size. The subsys id that is + mapping to the register of display function blocks is defined in the gce header + include/dt-bindings/gce/<chip>-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + maxItems: 1 + clocks: items: - description: SPLIT Clock @@ -48,6 +64,17 @@ required: - power-domains - clocks +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt8195-mdp3-split + + then: + required: + - mediatek,gce-client-reg + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml new file mode 100644 index 000000000000..03f31b009085 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-fg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Media Data Path 3 Film Grain + +maintainers: + - Matthias Brugger <matthias.bgg@gmail.com> + - Moudy Ho <moudy.ho@mediatek.com> + +description: + Film Grain (FG) is a Media Data Path 3 (MDP3) component used to add + the film grain according to the AOMedia Video 1 (AV1) standard. + +properties: + compatible: + enum: + - mediatek,mt8195-mdp3-fg + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4 arguments, + such as gce node, subsys id, offset and register size. The subsys id that is + mapping to the register of display function blocks is defined in the gce header + include/dt-bindings/gce/<chip>-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8195-clk.h> + #include <dt-bindings/gce/mt8195-gce.h> + + display@14002000 { + compatible = "mediatek,mt8195-mdp3-fg"; + reg = <0x14002000 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_FG>; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml new file mode 100644 index 000000000000..d4609bba6578 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-hdr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Media Data Path 3 HDR + +maintainers: + - Matthias Brugger <matthias.bgg@gmail.com> + - Moudy Ho <moudy.ho@mediatek.com> + +description: + A Media Data Path 3 (MDP3) component used to perform conversion from + High Dynamic Range (HDR) to Standard Dynamic Range (SDR). + +properties: + compatible: + enum: + - mediatek,mt8195-mdp3-hdr + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4 arguments, + such as gce node, subsys id, offset and register size. The subsys id that is + mapping to the register of display function blocks is defined in the gce header + include/dt-bindings/gce/<chip>-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8195-clk.h> + #include <dt-bindings/gce/mt8195-gce.h> + + display@14004000 { + compatible = "mediatek,mt8195-mdp3-hdr"; + reg = <0x14004000 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_HDR>; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml index 7032c7e15039..59db8306485b 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml @@ -20,8 +20,14 @@ description: | properties: compatible: - items: - - const: mediatek,mt8183-mdp3-rdma + oneOf: + - enum: + - mediatek,mt8183-mdp3-rdma + - mediatek,mt8195-mdp3-rdma + - mediatek,mt8195-vdo1-rdma + - items: + - const: mediatek,mt8188-vdo1-rdma + - const: mediatek,mt8195-vdo1-rdma reg: maxItems: 1 @@ -45,6 +51,14 @@ properties: include/dt-bindings/gce/<chip>-gce.h of each chips. $ref: /schemas/types.yaml#/definitions/uint32-array + mediatek,scp: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the System Control Processor (SCP) used for initializing + and stopping the MDP3, for sending frame data locations to the MDP3's + VPU and to install Inter-Processor Interrupt handlers to control + processing states. + power-domains: maxItems: 1 @@ -52,6 +66,7 @@ properties: items: - description: RDMA clock - description: RSZ clock + minItems: 1 iommus: maxItems: 1 @@ -60,16 +75,72 @@ properties: items: - description: used for 1st data pipe from RDMA - description: used for 2nd data pipe from RDMA + - description: used for 3rd data pipe from RDMA + - description: used for 4th data pipe from RDMA + - description: used for the data pipe from SPLIT + minItems: 1 + + interrupts: + maxItems: 1 + + '#dma-cells': + const: 1 required: - compatible - reg - mediatek,gce-client-reg - - mediatek,gce-events - power-domains - clocks - iommus - - mboxes + - '#dma-cells' + +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt8183-mdp3-rdma + + then: + properties: + clocks: + minItems: 2 + + mboxes: + minItems: 2 + + required: + - mboxes + - mediatek,gce-events + + - if: + properties: + compatible: + contains: + const: mediatek,mt8195-mdp3-rdma + + then: + properties: + clocks: + maxItems: 1 + + mboxes: + minItems: 5 + + required: + - mediatek,gce-events + + - if: + properties: + compatible: + contains: + const: mediatek,mt8195-vdo1-rdma + + then: + properties: + clocks: + maxItems: 1 additionalProperties: false @@ -80,16 +151,17 @@ examples: #include <dt-bindings/power/mt8183-power.h> #include <dt-bindings/memory/mt8183-larb-port.h> - mdp3_rdma0: mdp3-rdma0@14001000 { - compatible = "mediatek,mt8183-mdp3-rdma"; - reg = <0x14001000 0x1000>; - mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; - mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>, - <CMDQ_EVENT_MDP_RDMA0_EOF>; - power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; - clocks = <&mmsys CLK_MM_MDP_RDMA0>, - <&mmsys CLK_MM_MDP_RSZ1>; - iommus = <&iommu>; - mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>, - <&gce 21 CMDQ_THR_PRIO_LOWEST>; + dma-controller@14001000 { + compatible = "mediatek,mt8183-mdp3-rdma"; + reg = <0x14001000 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>, + <CMDQ_EVENT_MDP_RDMA0_EOF>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_RDMA0>, + <&mmsys CLK_MM_MDP_RSZ1>; + iommus = <&iommu>; + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>, + <&gce 21 CMDQ_THR_PRIO_LOWEST>; + #dma-cells = <1>; }; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml index 78f9de6192ef..f5676bec4326 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml @@ -15,9 +15,13 @@ description: | properties: compatible: - items: + oneOf: - enum: - mediatek,mt8183-mdp3-rsz + - items: + - enum: + - mediatek,mt8195-mdp3-rsz + - const: mediatek,mt8183-mdp3-rsz reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml new file mode 100644 index 000000000000..d815bea29154 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-stitch.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Media Data Path 3 STITCH + +maintainers: + - Matthias Brugger <matthias.bgg@gmail.com> + - Moudy Ho <moudy.ho@mediatek.com> + +description: + One of Media Data Path 3 (MDP3) components used to combine multiple video frame + with overlapping fields of view to produce a segmented panorame. + +properties: + compatible: + enum: + - mediatek,mt8195-mdp3-stitch + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4 arguments, + such as gce node, subsys id, offset and register size. The subsys id that is + mapping to the register of display function blocks is defined in the gce header + include/dt-bindings/gce/<chip>-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8195-clk.h> + #include <dt-bindings/gce/mt8195-gce.h> + + display@14003000 { + compatible = "mediatek,mt8195-mdp3-stitch"; + reg = <0x14003000 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_STITCH>; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml new file mode 100644 index 000000000000..14ea556d4f82 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-tcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Media Data Path 3 Tone Curve Conversion + +maintainers: + - Matthias Brugger <matthias.bgg@gmail.com> + +description: + Tone Curve Conversion (TCC) is one of Media Profile Path 3 (MDP3) components. + It is used to handle the tone mapping of various gamma curves in order to + achieve HDR10 effects. This helps adapt the content to the color and + brightness range that standard display devices typically support. + +properties: + compatible: + enum: + - mediatek,mt8195-mdp3-tcc + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4 arguments, + such as gce node, subsys id, offset and register size. The subsys id that is + mapping to the register of display function blocks is defined in the gce header + include/dt-bindings/gce/<chip>-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8195-clk.h> + #include <dt-bindings/gce/mt8195-gce.h> + + display@1400b000 { + compatible = "mediatek,mt8195-mdp3-tcc"; + reg = <0x1400b000 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_TCC>; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml new file mode 100644 index 000000000000..8ab7f2d8e148 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-tdshp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Media Data Path 3 Two-Dimensional Sharpness + +maintainers: + - Matthias Brugger <matthias.bgg@gmail.com> + - Moudy Ho <moudy.ho@mediatek.com> + +description: + Two-Dimensional Sharpness (TDSHP) is a Media Profile Path 3 (MDP3) component + used to perform image edge sharpening and enhance vividness and contrast. + +properties: + compatible: + enum: + - mediatek,mt8195-mdp3-tdshp + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4 arguments, + such as gce node, subsys id, offset and register size. The subsys id that is + mapping to the register of display function blocks is defined in the gce header + include/dt-bindings/gce/<chip>-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8195-clk.h> + #include <dt-bindings/gce/mt8195-gce.h> + + display@14007000 { + compatible = "mediatek,mt8195-mdp3-tdshp"; + reg = <0x14007000 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml index 0baa77198fa2..53a679338402 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml @@ -15,9 +15,13 @@ description: | properties: compatible: - items: + oneOf: - enum: - mediatek,mt8183-mdp3-wrot + - items: + - enum: + - mediatek,mt8195-mdp3-wrot + - const: mediatek,mt8183-mdp3-wrot reg: maxItems: 1 @@ -50,6 +54,9 @@ properties: iommus: maxItems: 1 + '#dma-cells': + const: 1 + required: - compatible - reg @@ -58,6 +65,7 @@ required: - power-domains - clocks - iommus + - '#dma-cells' additionalProperties: false @@ -68,13 +76,14 @@ examples: #include <dt-bindings/power/mt8183-power.h> #include <dt-bindings/memory/mt8183-larb-port.h> - mdp3_wrot0: mdp3-wrot0@14005000 { - compatible = "mediatek,mt8183-mdp3-wrot"; - reg = <0x14005000 0x1000>; - mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; - mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>, - <CMDQ_EVENT_MDP_WROT0_EOF>; - power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; - clocks = <&mmsys CLK_MM_MDP_WROT0>; - iommus = <&iommu>; + dma-controller@14005000 { + compatible = "mediatek,mt8183-mdp3-wrot"; + reg = <0x14005000 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>, + <CMDQ_EVENT_MDP_WROT0_EOF>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_WROT0>; + iommus = <&iommu>; + #dma-cells = <1>; }; diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml index a06ac2177444..4737e5f45d54 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml @@ -41,7 +41,6 @@ properties: - mediatek,mt8173-pwrap - mediatek,mt8183-pwrap - mediatek,mt8186-pwrap - - mediatek,mt8188-pwrap - mediatek,mt8195-pwrap - mediatek,mt8365-pwrap - mediatek,mt8516-pwrap @@ -50,6 +49,11 @@ properties: - mediatek,mt8186-pwrap - mediatek,mt8195-pwrap - const: syscon + - items: + - enum: + - mediatek,mt8188-pwrap + - const: mediatek,mt8195-pwrap + - const: syscon reg: minItems: 1 diff --git a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml index 7eda63d5682f..742b91d1d28e 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml @@ -22,8 +22,10 @@ properties: compatible: enum: - mediatek,mt8183-svs + - mediatek,mt8186-svs - mediatek,mt8188-svs - mediatek,mt8192-svs + - mediatek,mt8195-svs reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt2701-audio.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt2701-audio.yaml new file mode 100644 index 000000000000..45382c4d86aa --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mediatek,mt2701-audio.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mt2701-audio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Audio Front End (AFE) PCM controller for mt2701 + +description: + The AFE PCM node must be a subnode of the MediaTek audsys device tree node. + +maintainers: + - Eugen Hristev <eugen.hristev@collabora.com> + +properties: + compatible: + enum: + - mediatek,mt2701-audio + - mediatek,mt7622-audio + + interrupts: + items: + - description: AFE interrupt + - description: ASYS interrupt + + interrupt-names: + items: + - const: afe + - const: asys + + power-domains: + maxItems: 1 + + clocks: + items: + - description: audio infra sys clock + - description: top audio mux 1 + - description: top audio mux 2 + - description: top audio sys a1 clock + - description: top audio sys a2 clock + - description: i2s0 source selection + - description: i2s1 source selection + - description: i2s2 source selection + - description: i2s3 source selection + - description: i2s0 source divider + - description: i2s1 source divider + - description: i2s2 source divider + - description: i2s3 source divider + - description: i2s0 master clock + - description: i2s1 master clock + - description: i2s2 master clock + - description: i2s3 master clock + - description: i2so0 hopping clock + - description: i2so1 hopping clock + - description: i2so2 hopping clock + - description: i2so3 hopping clock + - description: i2si0 hopping clock + - description: i2si1 hopping clock + - description: i2si2 hopping clock + - description: i2si3 hopping clock + - description: asrc0 output clock + - description: asrc1 output clock + - description: asrc2 output clock + - description: asrc3 output clock + - description: audio front end pd clock + - description: audio front end conn pd clock + - description: top audio a1 sys pd + - description: top audio a2 sys pd + - description: audio merge interface pd + + clock-names: + items: + - const: infra_sys_audio_clk + - const: top_audio_mux1_sel + - const: top_audio_mux2_sel + - const: top_audio_a1sys_hp + - const: top_audio_a2sys_hp + - const: i2s0_src_sel + - const: i2s1_src_sel + - const: i2s2_src_sel + - const: i2s3_src_sel + - const: i2s0_src_div + - const: i2s1_src_div + - const: i2s2_src_div + - const: i2s3_src_div + - const: i2s0_mclk_en + - const: i2s1_mclk_en + - const: i2s2_mclk_en + - const: i2s3_mclk_en + - const: i2so0_hop_ck + - const: i2so1_hop_ck + - const: i2so2_hop_ck + - const: i2so3_hop_ck + - const: i2si0_hop_ck + - const: i2si1_hop_ck + - const: i2si2_hop_ck + - const: i2si3_hop_ck + - const: asrc0_out_ck + - const: asrc1_out_ck + - const: asrc2_out_ck + - const: asrc3_out_ck + - const: audio_afe_pd + - const: audio_afe_conn_pd + - const: audio_a1sys_pd + - const: audio_a2sys_pd + - const: audio_mrgif_pd + +required: + - compatible + - interrupts + - interrupt-names + - power-domains + - clocks + - clock-names + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt deleted file mode 100644 index f548e6a58240..000000000000 --- a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt +++ /dev/null @@ -1,146 +0,0 @@ -Mediatek AFE PCM controller for mt2701 - -Required properties: -- compatible: should be one of the following. - - "mediatek,mt2701-audio" - - "mediatek,mt7622-audio" -- interrupts: should contain AFE and ASYS interrupts -- interrupt-names: should be "afe" and "asys" -- power-domains: should define the power domain -- clocks: Must contain an entry for each entry in clock-names - See ../clocks/clock-bindings.txt for details -- clock-names: should have these clock names: - "infra_sys_audio_clk", - "top_audio_mux1_sel", - "top_audio_mux2_sel", - "top_audio_a1sys_hp", - "top_audio_a2sys_hp", - "i2s0_src_sel", - "i2s1_src_sel", - "i2s2_src_sel", - "i2s3_src_sel", - "i2s0_src_div", - "i2s1_src_div", - "i2s2_src_div", - "i2s3_src_div", - "i2s0_mclk_en", - "i2s1_mclk_en", - "i2s2_mclk_en", - "i2s3_mclk_en", - "i2so0_hop_ck", - "i2so1_hop_ck", - "i2so2_hop_ck", - "i2so3_hop_ck", - "i2si0_hop_ck", - "i2si1_hop_ck", - "i2si2_hop_ck", - "i2si3_hop_ck", - "asrc0_out_ck", - "asrc1_out_ck", - "asrc2_out_ck", - "asrc3_out_ck", - "audio_afe_pd", - "audio_afe_conn_pd", - "audio_a1sys_pd", - "audio_a2sys_pd", - "audio_mrgif_pd"; -- assigned-clocks: list of input clocks and dividers for the audio system. - See ../clocks/clock-bindings.txt for details. -- assigned-clocks-parents: parent of input clocks of assigned clocks. -- assigned-clock-rates: list of clock frequencies of assigned clocks. - -Must be a subnode of MediaTek audsys device tree node. -See ../arm/mediatek/mediatek,audsys.txt for details about the parent node. - -Example: - - audsys: audio-subsystem@11220000 { - compatible = "mediatek,mt2701-audsys", "syscon"; - ... - - afe: audio-controller { - compatible = "mediatek,mt2701-audio"; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "afe", "asys"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; - - clocks = <&infracfg CLK_INFRA_AUDIO>, - <&topckgen CLK_TOP_AUD_MUX1_SEL>, - <&topckgen CLK_TOP_AUD_MUX2_SEL>, - <&topckgen CLK_TOP_AUD_48K_TIMING>, - <&topckgen CLK_TOP_AUD_44K_TIMING>, - <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, - <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, - <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, - <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, - <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, - <&topckgen CLK_TOP_AUD_I2S1_MCLK>, - <&topckgen CLK_TOP_AUD_I2S2_MCLK>, - <&topckgen CLK_TOP_AUD_I2S3_MCLK>, - <&topckgen CLK_TOP_AUD_I2S4_MCLK>, - <&audsys CLK_AUD_I2SO1>, - <&audsys CLK_AUD_I2SO2>, - <&audsys CLK_AUD_I2SO3>, - <&audsys CLK_AUD_I2SO4>, - <&audsys CLK_AUD_I2SIN1>, - <&audsys CLK_AUD_I2SIN2>, - <&audsys CLK_AUD_I2SIN3>, - <&audsys CLK_AUD_I2SIN4>, - <&audsys CLK_AUD_ASRCO1>, - <&audsys CLK_AUD_ASRCO2>, - <&audsys CLK_AUD_ASRCO3>, - <&audsys CLK_AUD_ASRCO4>, - <&audsys CLK_AUD_AFE>, - <&audsys CLK_AUD_AFE_CONN>, - <&audsys CLK_AUD_A1SYS>, - <&audsys CLK_AUD_A2SYS>, - <&audsys CLK_AUD_AFE_MRGIF>; - - clock-names = "infra_sys_audio_clk", - "top_audio_mux1_sel", - "top_audio_mux2_sel", - "top_audio_a1sys_hp", - "top_audio_a2sys_hp", - "i2s0_src_sel", - "i2s1_src_sel", - "i2s2_src_sel", - "i2s3_src_sel", - "i2s0_src_div", - "i2s1_src_div", - "i2s2_src_div", - "i2s3_src_div", - "i2s0_mclk_en", - "i2s1_mclk_en", - "i2s2_mclk_en", - "i2s3_mclk_en", - "i2so0_hop_ck", - "i2so1_hop_ck", - "i2so2_hop_ck", - "i2so3_hop_ck", - "i2si0_hop_ck", - "i2si1_hop_ck", - "i2si2_hop_ck", - "i2si3_hop_ck", - "asrc0_out_ck", - "asrc1_out_ck", - "asrc2_out_ck", - "asrc3_out_ck", - "audio_afe_pd", - "audio_afe_conn_pd", - "audio_a1sys_pd", - "audio_a2sys_pd", - "audio_mrgif_pd"; - - assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, - <&topckgen CLK_TOP_AUD_MUX2_SEL>, - <&topckgen CLK_TOP_AUD_MUX1_DIV>, - <&topckgen CLK_TOP_AUD_MUX2_DIV>; - assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, - <&topckgen CLK_TOP_AUD2PLL_90M>; - assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; - }; - }; diff --git a/Documentation/devicetree/bindings/thermal/mediatek,thermal.yaml b/Documentation/devicetree/bindings/thermal/mediatek,thermal.yaml new file mode 100644 index 000000000000..d96a2e32bd8f --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/mediatek,thermal.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/mediatek,thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek thermal controller for on-SoC temperatures + +maintainers: + - Sascha Hauer <s.hauer@pengutronix.de> + +description: + This device does not have its own ADC, instead it directly controls the AUXADC + via AHB bus accesses. For this reason it needs phandles to the AUXADC. Also it + controls a mux in the apmixedsys register space via AHB bus accesses, so a + phandle to the APMIXEDSYS is also needed. + +allOf: + - $ref: thermal-sensor.yaml# + +properties: + compatible: + enum: + - mediatek,mt2701-thermal + - mediatek,mt2712-thermal + - mediatek,mt7622-thermal + - mediatek,mt7981-thermal + - mediatek,mt7986-thermal + - mediatek,mt8173-thermal + - mediatek,mt8183-thermal + - mediatek,mt8365-thermal + - mediatek,mt8516-thermal + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Main clock needed for register access + - description: The AUXADC clock + + clock-names: + items: + - const: therm + - const: auxadc + + mediatek,auxadc: + $ref: /schemas/types.yaml#/definitions/phandle + description: A phandle to the AUXADC which the thermal controller uses + + mediatek,apmixedsys: + $ref: /schemas/types.yaml#/definitions/phandle + description: A phandle to the APMIXEDSYS controller + + resets: + description: Reset controller controlling the thermal controller + + nvmem-cells: + items: + - description: + NVMEM cell with EEPROMA phandle to the calibration data provided by an + NVMEM device. If unspecified default values shall be used. + + nvmem-cell-names: + items: + - const: calibration-data + +required: + - reg + - interrupts + - clocks + - clock-names + - mediatek,auxadc + - mediatek,apmixedsys + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/mt8173-clk.h> + #include <dt-bindings/reset/mt8173-resets.h> + + thermal@1100b000 { + compatible = "mediatek,mt8173-thermal"; + reg = <0x1100b000 0x1000>; + interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; + clock-names = "therm", "auxadc"; + resets = <&pericfg MT8173_PERI_THERM_SW_RST>; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + nvmem-cells = <&thermal_calibration_data>; + nvmem-cell-names = "calibration-data"; + #thermal-sensor-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt deleted file mode 100644 index ac39c7156fde..000000000000 --- a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt +++ /dev/null @@ -1,52 +0,0 @@ -* Mediatek Thermal - -This describes the device tree binding for the Mediatek thermal controller -which measures the on-SoC temperatures. This device does not have its own ADC, -instead it directly controls the AUXADC via AHB bus accesses. For this reason -this device needs phandles to the AUXADC. Also it controls a mux in the -apmixedsys register space via AHB bus accesses, so a phandle to the APMIXEDSYS -is also needed. - -Required properties: -- compatible: - - "mediatek,mt8173-thermal" : For MT8173 family of SoCs - - "mediatek,mt2701-thermal" : For MT2701 family of SoCs - - "mediatek,mt2712-thermal" : For MT2712 family of SoCs - - "mediatek,mt7622-thermal" : For MT7622 SoC - - "mediatek,mt7981-thermal", "mediatek,mt7986-thermal" : For MT7981 SoC - - "mediatek,mt7986-thermal" : For MT7986 SoC - - "mediatek,mt8183-thermal" : For MT8183 family of SoCs - - "mediatek,mt8365-thermal" : For MT8365 family of SoCs - - "mediatek,mt8516-thermal", "mediatek,mt2701-thermal : For MT8516 family of SoCs -- reg: Address range of the thermal controller -- interrupts: IRQ for the thermal controller -- clocks, clock-names: Clocks needed for the thermal controller. required - clocks are: - "therm": Main clock needed for register access - "auxadc": The AUXADC clock -- mediatek,auxadc: A phandle to the AUXADC which the thermal controller uses -- mediatek,apmixedsys: A phandle to the APMIXEDSYS controller. -- #thermal-sensor-cells : Should be 0. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for a description. - -Optional properties: -- resets: Reference to the reset controller controlling the thermal controller. -- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If - unspecified default values shall be used. -- nvmem-cell-names: Should be "calibration-data" - -Example: - - thermal: thermal@1100b000 { - #thermal-sensor-cells = <1>; - compatible = "mediatek,mt8173-thermal"; - reg = <0 0x1100b000 0 0x1000>; - interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; - clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; - clock-names = "therm", "auxadc"; - resets = <&pericfg MT8173_PERI_THERM_SW_RST>; - reset-names = "therm"; - mediatek,auxadc = <&auxadc>; - mediatek,apmixedsys = <&apmixedsys>; - nvmem-cells = <&thermal_calibration_data>; - nvmem-cell-names = "calibration-data"; - }; |