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authorLinus Torvalds <torvalds@linux-foundation.org>2020-04-03 03:32:52 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2020-04-03 03:32:52 +0300
commitbef7b2a7be28638770972ab2709adf11d601c11a (patch)
treec6608ceca8e2f36ec6e4ccf9a46959a88036a8ef /Documentation
parent79f51b7b9c4719303f758ae8406c4e5997ed6aa3 (diff)
parent8967918e7cee84d8b781feec38286c7d3c1c05da (diff)
downloadlinux-bef7b2a7be28638770972ab2709adf11d601c11a.tar.xz
Merge tag 'devicetree-for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring: - Unit test for overlays with GPIO hogs - Improve dma-ranges parsing to handle dma-ranges with multiple entries - Update dtc to upstream version v1.6.0-2-g87a656ae5ff9 - Improve overlay error reporting - Device link support for power-domains and hwlocks bindings - Add vendor prefixes for Beacon, Topwise, ENE, Dell, SG Micro, Elida, PocketBook, Xiaomi, Linutronix, OzzMaker, Waveshare Electronics, and ITE Tech - Add deprecated Marvell vendor prefix 'mrvl' - A bunch of binding conversions to DT schema continues. Of note, the common serial and USB connector bindings are converted. - Add more Arm CPU compatibles - Drop Mark Rutland as DT maintainer :( * tag 'devicetree-for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (106 commits) MAINTAINERS: drop an old reference to stm32 pwm timers doc MAINTAINERS: dt: update etnaviv file reference dt-bindings: usb: dwc2: fix bindings for amlogic, meson-gxbb-usb dt-bindings: uniphier-system-bus: fix warning in the example dt-bindings: display: meson-vpu: fix indentation of reg-names' "items" dt-bindings: iio: Fix adi, ltc2983 uint64-matrix schema constraints dt-bindings: power: Fix example for power-domain dt-bindings: arm: Add some constraints for PSCI nodes of: some unittest overlays not untracked of: gpio unittest kfree() wrong object dt-bindings: phy: convert phy-rockchip-inno-usb2 bindings to yaml dt-bindings: serial: sh-sci: Convert to json-schema dt-bindings: serial: Document serialN aliases dt-bindings: thermal: tsens: Set 'additionalProperties: false' dt-bindings: thermal: tsens: Fix nvmem-cell-names schema dt-bindings: vendor-prefixes: Add Beacon vendor prefix dt-bindings: vendor-prefixes: Add Topwise of: of_private.h: Replace zero-length array with flexible-array member docs: dt: fix a broken reference to input.yaml docs: dt: fix references to ap806-system-controller.txt ...
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml2
-rw-r--r--Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml2
-rw-r--r--Documentation/devicetree/bindings/arm/cpus.yaml11
-rw-r--r--Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt2
-rw-r--r--Documentation/devicetree/bindings/arm/l2c2x0.yaml45
-rw-r--r--Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml5
-rw-r--r--Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml2
-rw-r--r--Documentation/devicetree/bindings/arm/pmu.yaml41
-rw-r--r--Documentation/devicetree/bindings/arm/psci.yaml5
-rw-r--r--Documentation/devicetree/bindings/arm/renesas,prr.yaml2
-rw-r--r--Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml2
-rw-r--r--Documentation/devicetree/bindings/arm/samsung/pmu.yaml2
-rw-r--r--Documentation/devicetree/bindings/arm/samsung/samsung-secure-firmware.yaml2
-rw-r--r--Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt60
-rw-r--r--Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml102
-rw-r--r--Documentation/devicetree/bindings/arm/socionext/uniphier.txt47
-rw-r--r--Documentation/devicetree/bindings/arm/socionext/uniphier.yaml61
-rw-r--r--Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml2
-rw-r--r--Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml71
-rw-r--r--Documentation/devicetree/bindings/ata/sata_rcar.txt36
-rw-r--r--Documentation/devicetree/bindings/bus/socionext,uniphier-system-bus.yaml96
-rw-r--r--Documentation/devicetree/bindings/bus/uniphier-system-bus.txt66
-rw-r--r--Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml54
-rw-r--r--Documentation/devicetree/bindings/clock/clock-bindings.txt2
-rw-r--r--Documentation/devicetree/bindings/clock/fsl,plldig.yaml5
-rw-r--r--Documentation/devicetree/bindings/clock/imx8mn-clock.yaml2
-rw-r--r--Documentation/devicetree/bindings/clock/imx8mp-clock.yaml2
-rw-r--r--Documentation/devicetree/bindings/clock/milbeaut-clock.yaml2
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml2
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml2
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml2
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml2
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml2
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml2
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml2
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc.yaml2
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,mmcc.yaml2
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml2
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml2
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml2
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,sc7180-gpucc.yaml2
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml2
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml2
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,sdm845-gpucc.yaml2
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,sdm845-videocc.yaml2
-rw-r--r--Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml94
-rw-r--r--Documentation/devicetree/bindings/clock/uniphier-clock.txt132
-rw-r--r--Documentation/devicetree/bindings/connector/samsung,usb-connector-11pin.txt2
-rw-r--r--Documentation/devicetree/bindings/connector/usb-connector.txt135
-rw-r--r--Documentation/devicetree/bindings/connector/usb-connector.yaml206
-rw-r--r--Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml8
-rw-r--r--Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt36
-rw-r--r--Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml2
-rw-r--r--Documentation/devicetree/bindings/dma/socionext,uniphier-mio-dmac.yaml63
-rw-r--r--Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt25
-rw-r--r--Documentation/devicetree/bindings/dsp/fsl,dsp.yaml2
-rw-r--r--Documentation/devicetree/bindings/eeprom/at24.yaml2
-rw-r--r--Documentation/devicetree/bindings/example-schema.yaml4
-rw-r--r--Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml3
-rw-r--r--Documentation/devicetree/bindings/gnss/gnss.txt2
-rw-r--r--Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml2
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio-mvebu.txt2
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio-uniphier.txt51
-rw-r--r--Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml94
-rw-r--r--Documentation/devicetree/bindings/gpio/xylon,logicvc-gpio.yaml2
-rw-r--r--Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml8
-rw-r--r--Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml5
-rw-r--r--Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml2
-rw-r--r--Documentation/devicetree/bindings/gpu/samsung-rotator.yaml2
-rw-r--r--Documentation/devicetree/bindings/gpu/vivante,gc.yaml69
-rw-r--r--Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml2
-rw-r--r--Documentation/devicetree/bindings/hwmon/adi,ltc2947.yaml2
-rw-r--r--Documentation/devicetree/bindings/hwmon/pmbus/ti,ucd90320.yaml2
-rw-r--r--Documentation/devicetree/bindings/hwmon/ti,tmp513.yaml2
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-rk3x.txt68
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml136
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-uniphier-f.txt25
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-uniphier.txt25
-rw-r--r--Documentation/devicetree/bindings/i2c/socionext,uniphier-fi2c.yaml50
-rw-r--r--Documentation/devicetree/bindings/i2c/socionext,uniphier-i2c.yaml50
-rw-r--r--Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml10
-rw-r--r--Documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml2
-rw-r--r--Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml1
-rw-r--r--Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml2
-rw-r--r--Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml2
-rw-r--r--Documentation/devicetree/bindings/iio/adc/lltc,ltc2496.yaml2
-rw-r--r--Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml2
-rw-r--r--Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml2
-rw-r--r--Documentation/devicetree/bindings/iio/chemical/plantower,pms7003.yaml2
-rw-r--r--Documentation/devicetree/bindings/iio/chemical/sensirion,sps30.yaml2
-rw-r--r--Documentation/devicetree/bindings/iio/dac/lltc,ltc1660.yaml2
-rw-r--r--Documentation/devicetree/bindings/iio/light/adux1020.yaml2
-rw-r--r--Documentation/devicetree/bindings/iio/light/bh1750.yaml2
-rw-r--r--Documentation/devicetree/bindings/iio/light/isl29018.yaml2
-rw-r--r--Documentation/devicetree/bindings/iio/light/noa1305.yaml2
-rw-r--r--Documentation/devicetree/bindings/iio/light/stk33xx.yaml2
-rw-r--r--Documentation/devicetree/bindings/iio/light/tsl2583.yaml2
-rw-r--r--Documentation/devicetree/bindings/iio/light/tsl2772.yaml2
-rw-r--r--Documentation/devicetree/bindings/iio/light/veml6030.yaml2
-rw-r--r--Documentation/devicetree/bindings/iio/pressure/asc,dlhl60d.yaml2
-rw-r--r--Documentation/devicetree/bindings/iio/pressure/bmp085.yaml5
-rw-r--r--Documentation/devicetree/bindings/iio/proximity/devantech-srf04.yaml2
-rw-r--r--Documentation/devicetree/bindings/iio/proximity/parallax-ping.yaml2
-rw-r--r--Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml40
-rw-r--r--Documentation/devicetree/bindings/input/gpio-vibrator.yaml2
-rw-r--r--Documentation/devicetree/bindings/input/max77650-onkey.yaml3
-rw-r--r--Documentation/devicetree/bindings/input/st,stpmic1-onkey.txt28
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml2
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/msi.txt2
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.txt32
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.yaml61
-rw-r--r--Documentation/devicetree/bindings/iommu/samsung,sysmmu.yaml2
-rw-r--r--Documentation/devicetree/bindings/leds/common.yaml4
-rw-r--r--Documentation/devicetree/bindings/leds/leds-max77650.yaml3
-rw-r--r--Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml3
-rw-r--r--Documentation/devicetree/bindings/mailbox/amlogic,meson-gxbb-mhu.yaml2
-rw-r--r--Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml2
-rw-r--r--Documentation/devicetree/bindings/media/amlogic,meson-gx-ao-cec.yaml11
-rw-r--r--Documentation/devicetree/bindings/media/renesas,ceu.yaml2
-rw-r--r--Documentation/devicetree/bindings/media/renesas,vin.txt217
-rw-r--r--Documentation/devicetree/bindings/media/renesas,vin.yaml402
-rw-r--r--Documentation/devicetree/bindings/mfd/max77650.yaml2
-rw-r--r--Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml5
-rw-r--r--Documentation/devicetree/bindings/mfd/st,stpmic1.txt61
-rw-r--r--Documentation/devicetree/bindings/mfd/st,stpmic1.yaml339
-rw-r--r--Documentation/devicetree/bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml2
-rw-r--r--Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml143
-rw-r--r--Documentation/devicetree/bindings/mmc/sdhci-cadence.txt80
-rw-r--r--Documentation/devicetree/bindings/mmc/socionext,uniphier-sd.yaml99
-rw-r--r--Documentation/devicetree/bindings/mmc/uniphier-sd.txt55
-rw-r--r--Documentation/devicetree/bindings/mtd/denali,nand.yaml148
-rw-r--r--Documentation/devicetree/bindings/mtd/denali-nand.txt61
-rw-r--r--Documentation/devicetree/bindings/net/broadcom-bluetooth.txt2
-rw-r--r--Documentation/devicetree/bindings/net/can/bosch,m_can.yaml144
-rw-r--r--Documentation/devicetree/bindings/net/can/can-transceiver.txt24
-rw-r--r--Documentation/devicetree/bindings/net/can/can-transceiver.yaml18
-rw-r--r--Documentation/devicetree/bindings/net/can/m_can.txt75
-rw-r--r--Documentation/devicetree/bindings/net/can/tcan4x5x.txt2
-rw-r--r--Documentation/devicetree/bindings/net/mediatek-bluetooth.txt2
-rw-r--r--Documentation/devicetree/bindings/net/qca,qca7000.txt2
-rw-r--r--Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml25
-rw-r--r--Documentation/devicetree/bindings/net/ti-bluetooth.txt3
-rw-r--r--Documentation/devicetree/bindings/phy/allwinner,sun50i-h6-usb3-phy.yaml2
-rw-r--r--Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml2
-rw-r--r--Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml2
-rw-r--r--Documentation/devicetree/bindings/phy/marvell,mmp3-hsic-phy.yaml2
-rw-r--r--Documentation/devicetree/bindings/phy/marvell,mmp3-usb-phy.yaml42
-rw-r--r--Documentation/devicetree/bindings/phy/phy-mmp3-usb.txt13
-rw-r--r--Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt81
-rw-r--r--Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml155
-rw-r--r--Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml2
-rw-r--r--Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml2
-rw-r--r--Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml2
-rw-r--r--Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml2
-rw-r--r--Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt27
-rw-r--r--Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml42
-rw-r--r--Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml2
-rw-r--r--Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml2
-rw-r--r--Documentation/devicetree/bindings/power/power-domain.yaml28
-rw-r--r--Documentation/devicetree/bindings/power/renesas,apmu.txt35
-rw-r--r--Documentation/devicetree/bindings/power/renesas,apmu.yaml55
-rw-r--r--Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt62
-rw-r--r--Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml73
-rw-r--r--Documentation/devicetree/bindings/power/reset/syscon-poweroff.yaml2
-rw-r--r--Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml2
-rw-r--r--Documentation/devicetree/bindings/power/supply/max77650-charger.yaml3
-rw-r--r--Documentation/devicetree/bindings/ptp/ptp-idtcm.yaml2
-rw-r--r--Documentation/devicetree/bindings/pwm/pwm-mediatek.txt5
-rw-r--r--Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml4
-rw-r--r--Documentation/devicetree/bindings/regulator/max77650-regulator.yaml5
-rw-r--r--Documentation/devicetree/bindings/regulator/st,stpmic1-regulator.txt64
-rw-r--r--Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml2
-rw-r--r--Documentation/devicetree/bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml2
-rw-r--r--Documentation/devicetree/bindings/reset/renesas,rst.txt48
-rw-r--r--Documentation/devicetree/bindings/reset/renesas,rst.yaml63
-rw-r--r--Documentation/devicetree/bindings/rng/amlogic,meson-rng.yaml2
-rw-r--r--Documentation/devicetree/bindings/rng/brcm,bcm2835.txt40
-rw-r--r--Documentation/devicetree/bindings/rng/brcm,bcm2835.yaml61
-rw-r--r--Documentation/devicetree/bindings/rtc/renesas,sh-rtc.yaml2
-rw-r--r--Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml2
-rw-r--r--Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml2
-rw-r--r--Documentation/devicetree/bindings/serial/fsl-imx-uart.txt2
-rw-r--r--Documentation/devicetree/bindings/serial/renesas,hscif.yaml135
-rw-r--r--Documentation/devicetree/bindings/serial/renesas,sci-serial.txt150
-rw-r--r--Documentation/devicetree/bindings/serial/renesas,sci.yaml69
-rw-r--r--Documentation/devicetree/bindings/serial/renesas,scif.yaml172
-rw-r--r--Documentation/devicetree/bindings/serial/renesas,scifa.yaml107
-rw-r--r--Documentation/devicetree/bindings/serial/renesas,scifb.yaml98
-rw-r--r--Documentation/devicetree/bindings/serial/serial.txt56
-rw-r--r--Documentation/devicetree/bindings/serial/serial.yaml131
-rw-r--r--Documentation/devicetree/bindings/serial/slave-device.txt45
-rw-r--r--Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml1
-rw-r--r--Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml46
-rw-r--r--Documentation/devicetree/bindings/serial/uniphier-uart.txt22
-rw-r--r--Documentation/devicetree/bindings/soc/amlogic/amlogic,canvas.yaml2
-rw-r--r--Documentation/devicetree/bindings/soc/imx/fsl,aips-bus.yaml47
-rw-r--r--Documentation/devicetree/bindings/sound/adi,adau7118.yaml2
-rw-r--r--Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml2
-rw-r--r--Documentation/devicetree/bindings/sound/renesas,fsi.yaml2
-rw-r--r--Documentation/devicetree/bindings/sound/samsung,odroid.yaml2
-rw-r--r--Documentation/devicetree/bindings/sound/samsung-i2s.yaml2
-rw-r--r--Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt36
-rw-r--r--Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml88
-rw-r--r--Documentation/devicetree/bindings/sram/qcom,ocmem.yaml14
-rw-r--r--Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml4
-rw-r--r--Documentation/devicetree/bindings/thermal/armada-thermal.txt2
-rw-r--r--Documentation/devicetree/bindings/thermal/qcom-tsens.yaml37
-rw-r--r--Documentation/devicetree/bindings/thermal/rcar-thermal.txt78
-rw-r--r--Documentation/devicetree/bindings/thermal/rcar-thermal.yaml139
-rw-r--r--Documentation/devicetree/bindings/timer/arm,arch_timer.yaml2
-rw-r--r--Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml4
-rw-r--r--Documentation/devicetree/bindings/timer/arm,global_timer.yaml2
-rw-r--r--Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml2
-rw-r--r--Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml2
-rw-r--r--Documentation/devicetree/bindings/trivial-devices.yaml6
-rw-r--r--Documentation/devicetree/bindings/usb/dwc2.yaml19
-rw-r--r--Documentation/devicetree/bindings/usb/exynos-usb.txt9
-rw-r--r--Documentation/devicetree/bindings/usb/fcs,fusb302.txt2
-rw-r--r--Documentation/devicetree/bindings/usb/generic.txt2
-rw-r--r--Documentation/devicetree/bindings/usb/mediatek,mtu3.txt2
-rw-r--r--Documentation/devicetree/bindings/usb/mediatek,musb.txt2
-rw-r--r--Documentation/devicetree/bindings/usb/richtek,rt1711h.txt2
-rw-r--r--Documentation/devicetree/bindings/usb/ti,hd3ss3220.txt2
-rw-r--r--Documentation/devicetree/bindings/usb/typec-tcpci.txt2
-rw-r--r--Documentation/devicetree/bindings/usb/usb-conn-gpio.txt4
-rw-r--r--Documentation/devicetree/bindings/vendor-prefixes.yaml27
-rw-r--r--Documentation/devicetree/bindings/watchdog/st,stpmic1-wdt.txt11
227 files changed, 4521 insertions, 2262 deletions
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml
index e4131fa42b26..572381306681 100644
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml
@@ -21,6 +21,8 @@ properties:
required:
- compatible
+additionalProperties: false
+
examples:
- |
clkmgr@ffd04000 {
diff --git a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml
index 853d7d2b56f5..66213bd95e6e 100644
--- a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml
+++ b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml
@@ -43,6 +43,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
ao-secure@140 {
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index 0d5b61056b10..470e003b7f8a 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -123,11 +123,18 @@ properties:
- arm,cortex-a12
- arm,cortex-a15
- arm,cortex-a17
+ - arm,cortex-a32
+ - arm,cortex-a34
+ - arm,cortex-a35
- arm,cortex-a53
- arm,cortex-a55
- arm,cortex-a57
+ - arm,cortex-a65
- arm,cortex-a72
- arm,cortex-a73
+ - arm,cortex-a75
+ - arm,cortex-a76
+ - arm,cortex-a77
- arm,cortex-m0
- arm,cortex-m0+
- arm,cortex-m1
@@ -136,6 +143,8 @@ properties:
- arm,cortex-r4
- arm,cortex-r5
- arm,cortex-r7
+ - arm,neoverse-e1
+ - arm,neoverse-n1
- brcm,brahma-b15
- brcm,brahma-b53
- brcm,vulcan
@@ -155,6 +164,8 @@ properties:
- nvidia,tegra194-carmel
- qcom,krait
- qcom,kryo
+ - qcom,kryo260
+ - qcom,kryo280
- qcom,kryo385
- qcom,kryo485
- qcom,scorpion
diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
index e07735a8c2c7..8cac6fafaab0 100644
--- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
@@ -164,7 +164,7 @@ Required properties:
- compatible: should be:
"fsl,imx8qxp-sc-key"
followed by "fsl,imx-sc-key";
-- linux,keycodes: See Documentation/devicetree/bindings/input/keys.txt
+- linux,keycodes: See Documentation/devicetree/bindings/input/input.yaml
Example (imx8qxp):
-------------
diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.yaml b/Documentation/devicetree/bindings/arm/l2c2x0.yaml
index 913a8cd8b2c0..5d1d50eea26e 100644
--- a/Documentation/devicetree/bindings/arm/l2c2x0.yaml
+++ b/Documentation/devicetree/bindings/arm/l2c2x0.yaml
@@ -29,27 +29,30 @@ allOf:
properties:
compatible:
- enum:
- - arm,pl310-cache
- - arm,l220-cache
- - arm,l210-cache
- # DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
- - bcm,bcm11351-a2-pl310-cache
- # For Broadcom bcm11351 chipset where an
- # offset needs to be added to the address before passing down to the L2
- # cache controller
- - brcm,bcm11351-a2-pl310-cache
- # Marvell Controller designed to be
- # compatible with the ARM one, with system cache mode (meaning
- # maintenance operations on L1 are broadcasted to the L2 and L2
- # performs the same operation).
- - marvell,aurora-system-cache
- # Marvell Controller designed to be
- # compatible with the ARM one with outer cache mode.
- - marvell,aurora-outer-cache
- # Marvell Tauros3 cache controller, compatible
- # with arm,pl310-cache controller.
- - marvell,tauros3-cache
+ oneOf:
+ - enum:
+ - arm,pl310-cache
+ - arm,l220-cache
+ - arm,l210-cache
+ # DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
+ - bcm,bcm11351-a2-pl310-cache
+ # For Broadcom bcm11351 chipset where an
+ # offset needs to be added to the address before passing down to the L2
+ # cache controller
+ - brcm,bcm11351-a2-pl310-cache
+ # Marvell Controller designed to be
+ # compatible with the ARM one, with system cache mode (meaning
+ # maintenance operations on L1 are broadcasted to the L2 and L2
+ # performs the same operation).
+ - marvell,aurora-system-cache
+ # Marvell Controller designed to be
+ # compatible with the ARM one with outer cache mode.
+ - marvell,aurora-outer-cache
+ - items:
+ # Marvell Tauros3 cache controller, compatible
+ # with arm,pl310-cache controller.
+ - const: marvell,tauros3-cache
+ - const: arm,pl310-cache
cache-level:
const: 2
diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
index 818dfe6de512..3235ec9e9bad 100644
--- a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
+++ b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
@@ -28,8 +28,11 @@ properties:
items:
- enum:
- mrvl,mmp2-brownstone
+ - olpc,xo-1.75
- const: mrvl,mmp2
- description: MMP3 based boards
items:
- - const: mrvl,mmp3
+ - enum:
+ - dell,wyse-ariel
+ - const: marvell,mmp3
...
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
index 79902f470e4b..c3a8604dfa80 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
@@ -43,6 +43,8 @@ required:
- reg-names
- interrupts
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml
index 52ae094ce330..97df36d301c9 100644
--- a/Documentation/devicetree/bindings/arm/pmu.yaml
+++ b/Documentation/devicetree/bindings/arm/pmu.yaml
@@ -20,27 +20,36 @@ properties:
items:
- enum:
- apm,potenza-pmu
- - arm,armv8-pmuv3
- - arm,cortex-a73-pmu
- - arm,cortex-a72-pmu
- - arm,cortex-a57-pmu
- - arm,cortex-a53-pmu
- - arm,cortex-a35-pmu
- - arm,cortex-a17-pmu
- - arm,cortex-a15-pmu
- - arm,cortex-a12-pmu
- - arm,cortex-a9-pmu
- - arm,cortex-a8-pmu
- - arm,cortex-a7-pmu
- - arm,cortex-a5-pmu
- - arm,arm11mpcore-pmu
- - arm,arm1176-pmu
+ - arm,armv8-pmuv3 # Only for s/w models
- arm,arm1136-pmu
+ - arm,arm1176-pmu
+ - arm,arm11mpcore-pmu
+ - arm,cortex-a5-pmu
+ - arm,cortex-a7-pmu
+ - arm,cortex-a8-pmu
+ - arm,cortex-a9-pmu
+ - arm,cortex-a12-pmu
+ - arm,cortex-a15-pmu
+ - arm,cortex-a17-pmu
+ - arm,cortex-a32-pmu
+ - arm,cortex-a34-pmu
+ - arm,cortex-a35-pmu
+ - arm,cortex-a53-pmu
+ - arm,cortex-a55-pmu
+ - arm,cortex-a57-pmu
+ - arm,cortex-a65-pmu
+ - arm,cortex-a72-pmu
+ - arm,cortex-a73-pmu
+ - arm,cortex-a75-pmu
+ - arm,cortex-a76-pmu
+ - arm,cortex-a77-pmu
+ - arm,neoverse-e1-pmu
+ - arm,neoverse-n1-pmu
- brcm,vulcan-pmu
- cavium,thunder-pmu
+ - qcom,krait-pmu
- qcom,scorpion-pmu
- qcom,scorpion-mp-pmu
- - qcom,krait-pmu
interrupts:
# Don't know how many CPUs, so no constraints to specify
diff --git a/Documentation/devicetree/bindings/arm/psci.yaml b/Documentation/devicetree/bindings/arm/psci.yaml
index 5e66934455bb..9247b58c26fc 100644
--- a/Documentation/devicetree/bindings/arm/psci.yaml
+++ b/Documentation/devicetree/bindings/arm/psci.yaml
@@ -32,6 +32,9 @@ description: |+
http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
properties:
+ $nodename:
+ const: psci
+
compatible:
oneOf:
- description:
@@ -141,6 +144,8 @@ allOf:
- cpu_off
- cpu_on
+additionalProperties: false
+
examples:
- |+
diff --git a/Documentation/devicetree/bindings/arm/renesas,prr.yaml b/Documentation/devicetree/bindings/arm/renesas,prr.yaml
index 7f8d17f33983..dd087643a9f8 100644
--- a/Documentation/devicetree/bindings/arm/renesas,prr.yaml
+++ b/Documentation/devicetree/bindings/arm/renesas,prr.yaml
@@ -27,6 +27,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
prr: chipid@ff000044 {
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml
index afcd70803c12..0425d333b50d 100644
--- a/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml
@@ -30,6 +30,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
chipid@10000000 {
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.yaml b/Documentation/devicetree/bindings/arm/samsung/pmu.yaml
index 73b56fc5bf58..c9651892710e 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.yaml
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.yaml
@@ -89,6 +89,8 @@ required:
- clock-names
- clocks
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/exynos5250.h>
diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-secure-firmware.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-secure-firmware.yaml
index 51d23b6f8a94..3d9abad3c749 100644
--- a/Documentation/devicetree/bindings/arm/samsung/samsung-secure-firmware.yaml
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-secure-firmware.yaml
@@ -23,6 +23,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
firmware@203f000 {
diff --git a/Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt b/Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt
deleted file mode 100644
index d27a646f48a9..000000000000
--- a/Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt
+++ /dev/null
@@ -1,60 +0,0 @@
-UniPhier outer cache controller
-
-UniPhier SoCs are integrated with a full-custom outer cache controller system.
-All of them have a level 2 cache controller, and some have a level 3 cache
-controller as well.
-
-Required properties:
-- compatible: should be "socionext,uniphier-system-cache"
-- reg: offsets and lengths of the register sets for the device. It should
- contain 3 regions: control register, revision register, operation register,
- in this order.
-- cache-unified: specifies the cache is a unified cache.
-- cache-size: specifies the size in bytes of the cache
-- cache-sets: specifies the number of associativity sets of the cache
-- cache-line-size: specifies the line size in bytes
-- cache-level: specifies the level in the cache hierarchy. The value should
- be 2 for L2 cache, 3 for L3 cache, etc.
-
-Optional properties:
-- next-level-cache: phandle to the next level cache if present. The next level
- cache should be also compatible with "socionext,uniphier-system-cache".
-
-The L2 cache must exist to use the L3 cache; the cache hierarchy must be
-indicated correctly with "next-level-cache" properties.
-
-Example 1 (system with L2):
- l2: l2-cache@500c0000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
- <0x506c0000 0x400>;
- cache-unified;
- cache-size = <0x80000>;
- cache-sets = <256>;
- cache-line-size = <128>;
- cache-level = <2>;
- };
-
-Example 2 (system with L2 and L3):
- l2: l2-cache@500c0000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
- <0x506c0000 0x400>;
- cache-unified;
- cache-size = <0x200000>;
- cache-sets = <512>;
- cache-line-size = <128>;
- cache-level = <2>;
- next-level-cache = <&l3>;
- };
-
- l3: l3-cache@500c8000 {
- compatible = "socionext,uniphier-system-cache";
- reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
- <0x506c8000 0x400>;
- cache-unified;
- cache-size = <0x400000>;
- cache-sets = <512>;
- cache-line-size = <256>;
- cache-level = <3>;
- };
diff --git a/Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml b/Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml
new file mode 100644
index 000000000000..2e765bb3e6f6
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UniPhier outer cache controller
+
+description: |
+ UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
+ controller system. All of them have a level 2 cache controller, and some
+ have a level 3 cache controller as well.
+
+maintainers:
+ - Masahiro Yamada <yamada.masahiro@socionext.com>
+
+properties:
+ compatible:
+ const: socionext,uniphier-system-cache
+
+ reg:
+ description: |
+ should contain 3 regions: control register, revision register,
+ operation register, in this order.
+ minItems: 3
+ maxItems: 3
+
+ interrupts:
+ description: |
+ Interrupts can be used to notify the completion of cache operations.
+ The number of interrupts should match to the number of CPU cores.
+ The specified interrupts correspond to CPU0, CPU1, ... in this order.
+ minItems: 1
+ maxItems: 4
+
+ cache-unified: true
+
+ cache-size: true
+
+ cache-sets: true
+
+ cache-line-size: true
+
+ cache-level:
+ minimum: 2
+ maximum: 3
+
+ next-level-cache: true
+
+allOf:
+ - $ref: /schemas/cache-controller.yaml#
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - cache-unified
+ - cache-size
+ - cache-sets
+ - cache-line-size
+ - cache-level
+
+examples:
+ - |
+ // System with L2.
+ cache-controller@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
+ cache-unified;
+ cache-size = <0x140000>;
+ cache-sets = <512>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ };
+ - |
+ // System with L2 and L3.
+ // L2 should specify the next level cache by 'next-level-cache'.
+ l2: cache-controller@500c0000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
+ interrupts = <0 190 4>, <0 191 4>;
+ cache-unified;
+ cache-size = <0x200000>;
+ cache-sets = <512>;
+ cache-line-size = <128>;
+ cache-level = <2>;
+ next-level-cache = <&l3>;
+ };
+
+ l3: cache-controller@500c8000 {
+ compatible = "socionext,uniphier-system-cache";
+ reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
+ interrupts = <0 174 4>, <0 175 4>;
+ cache-unified;
+ cache-size = <0x200000>;
+ cache-sets = <512>;
+ cache-line-size = <256>;
+ cache-level = <3>;
+ };
diff --git a/Documentation/devicetree/bindings/arm/socionext/uniphier.txt b/Documentation/devicetree/bindings/arm/socionext/uniphier.txt
deleted file mode 100644
index b3ed1033740e..000000000000
--- a/Documentation/devicetree/bindings/arm/socionext/uniphier.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-Socionext UniPhier SoC family
------------------------------
-
-Required properties in the root node:
- - compatible: should contain board and SoC compatible strings
-
-SoC and board compatible strings:
- (sorted chronologically)
-
- - LD4 SoC: "socionext,uniphier-ld4"
- - Reference Board: "socionext,uniphier-ld4-ref"
-
- - Pro4 SoC: "socionext,uniphier-pro4"
- - Reference Board: "socionext,uniphier-pro4-ref"
- - Ace Board: "socionext,uniphier-pro4-ace"
- - Sanji Board: "socionext,uniphier-pro4-sanji"
-
- - sLD8 SoC: "socionext,uniphier-sld8"
- - Reference Board: "socionext,uniphier-sld8-ref"
-
- - PXs2 SoC: "socionext,uniphier-pxs2"
- - Gentil Board: "socionext,uniphier-pxs2-gentil"
- - Vodka Board: "socionext,uniphier-pxs2-vodka"
-
- - LD6b SoC: "socionext,uniphier-ld6b"
- - Reference Board: "socionext,uniphier-ld6b-ref"
-
- - LD11 SoC: "socionext,uniphier-ld11"
- - Reference Board: "socionext,uniphier-ld11-ref"
- - Global Board: "socionext,uniphier-ld11-global"
-
- - LD20 SoC: "socionext,uniphier-ld20"
- - Reference Board: "socionext,uniphier-ld20-ref"
- - Global Board: "socionext,uniphier-ld20-global"
-
- - PXs3 SoC: "socionext,uniphier-pxs3"
- - Reference Board: "socionext,uniphier-pxs3-ref"
-
-Example:
-
-/dts-v1/;
-
-/ {
- compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20";
-
- ...
-};
diff --git a/Documentation/devicetree/bindings/arm/socionext/uniphier.yaml b/Documentation/devicetree/bindings/arm/socionext/uniphier.yaml
new file mode 100644
index 000000000000..65ad6d8a3c99
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/socionext/uniphier.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/socionext/uniphier.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier platform device tree bindings
+
+maintainers:
+ - Masahiro Yamada <yamada.masahiro@socionext.com>
+
+properties:
+ $nodename:
+ const: /
+ compatible:
+ oneOf:
+ - description: LD4 SoC boards
+ items:
+ - enum:
+ - socionext,uniphier-ld4-ref
+ - const: socionext,uniphier-ld4
+ - description: Pro4 SoC boards
+ items:
+ - enum:
+ - socionext,uniphier-pro4-ace
+ - socionext,uniphier-pro4-ref
+ - socionext,uniphier-pro4-sanji
+ - const: socionext,uniphier-pro4
+ - description: sLD8 SoC boards
+ items:
+ - enum:
+ - socionext,uniphier-sld8-ref
+ - const: socionext,uniphier-sld8
+ - description: PXs2 SoC boards
+ items:
+ - enum:
+ - socionext,uniphier-pxs2-gentil
+ - socionext,uniphier-pxs2-vodka
+ - const: socionext,uniphier-pxs2
+ - description: LD6b SoC boards
+ items:
+ - enum:
+ - socionext,uniphier-ld6b-ref
+ - const: socionext,uniphier-ld6b
+ - description: LD11 SoC boards
+ items:
+ - enum:
+ - socionext,uniphier-ld11-global
+ - socionext,uniphier-ld11-ref
+ - const: socionext,uniphier-ld11
+ - description: LD20 SoC boards
+ items:
+ - enum:
+ - socionext,uniphier-ld20-global
+ - socionext,uniphier-ld20-ref
+ - const: socionext,uniphier-ld20
+ - description: PXs3 SoC boards
+ items:
+ - enum:
+ - socionext,uniphier-pxs3-ref
+ - const: socionext,uniphier-pxs3
diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
index 0dedf94c8578..baff80197d5a 100644
--- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
+++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
@@ -29,6 +29,8 @@ required:
- reg
- clocks
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/stm32mp1-clks.h>
diff --git a/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml b/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml
new file mode 100644
index 000000000000..7b69831060d8
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/ata/renesas,rcar-sata.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Renesas R-Car Serial-ATA Interface
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - renesas,sata-r8a7779 # R-Car H1
+ - items:
+ - enum:
+ - renesas,sata-r8a7790-es1 # R-Car H2 ES1
+ - renesas,sata-r8a7790 # R-Car H2 other than ES1
+ - renesas,sata-r8a7791 # R-Car M2-W
+ - renesas,sata-r8a7793 # R-Car M2-N
+ - const: renesas,rcar-gen2-sata # generic R-Car Gen2
+ - items:
+ - enum:
+ - renesas,sata-r8a774b1 # RZ/G2N
+ - renesas,sata-r8a7795 # R-Car H3
+ - renesas,sata-r8a77965 # R-Car M3-N
+ - const: renesas,rcar-gen3-sata # generic R-Car Gen3 or RZ/G2
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ iommus:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7791-sysc.h>
+
+ sata@ee300000 {
+ compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
+ reg = <0xee300000 0x200000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 815>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 815>;
+ };
diff --git a/Documentation/devicetree/bindings/ata/sata_rcar.txt b/Documentation/devicetree/bindings/ata/sata_rcar.txt
deleted file mode 100644
index a2fbdc91570d..000000000000
--- a/Documentation/devicetree/bindings/ata/sata_rcar.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-* Renesas R-Car SATA
-
-Required properties:
-- compatible : should contain one or more of the following:
- - "renesas,sata-r8a774b1" for RZ/G2N
- - "renesas,sata-r8a7779" for R-Car H1
- - "renesas,sata-r8a7790-es1" for R-Car H2 ES1
- - "renesas,sata-r8a7790" for R-Car H2 other than ES1
- - "renesas,sata-r8a7791" for R-Car M2-W
- - "renesas,sata-r8a7793" for R-Car M2-N
- - "renesas,sata-r8a7795" for R-Car H3
- - "renesas,sata-r8a77965" for R-Car M3-N
- - "renesas,rcar-gen2-sata" for a generic R-Car Gen2
- compatible device
- - "renesas,rcar-gen3-sata" for a generic R-Car Gen3 or
- RZ/G2 compatible device
- - "renesas,rcar-sata" is deprecated
-
- When compatible with the generic version nodes
- must list the SoC-specific version corresponding
- to the platform first followed by the generic
- version.
-
-- reg : address and length of the SATA registers;
-- interrupts : must consist of one interrupt specifier.
-- clocks : must contain a reference to the functional clock.
-
-Example:
-
-sata0: sata@ee300000 {
- compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata";
- reg = <0 0xee300000 0 0x2000>;
- interrupt-parent = <&gic>;
- interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
-};
diff --git a/Documentation/devicetree/bindings/bus/socionext,uniphier-system-bus.yaml b/Documentation/devicetree/bindings/bus/socionext,uniphier-system-bus.yaml
new file mode 100644
index 000000000000..c4c9119e4a20
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/socionext,uniphier-system-bus.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UniPhier System Bus
+
+description: |
+ The UniPhier System Bus is an external bus that connects on-board devices to
+ the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
+ some control signals. It supports up to 8 banks (chip selects).
+
+ Before any access to the bus, the bus controller must be configured; the bus
+ controller registers provide the control for the translation from the offset
+ within each bank to the CPU-viewed address. The needed setup includes the
+ base address, the size of each bank. Optionally, some timing parameters can
+ be optimized for faster bus access.
+
+maintainers:
+ - Masahiro Yamada <yamada.masahiro@socionext.com>
+
+properties:
+ compatible:
+ const: socionext,uniphier-system-bus
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ description: |
+ The first cell is the bank number (chip select).
+ The second cell is the address offset within the bank.
+ const: 2
+
+ "#size-cells":
+ const: 1
+
+ ranges:
+ description: |
+ Provide address translation from the System Bus to the parent bus.
+
+ Note:
+ The address region(s) that can be assigned for the System Bus is
+ implementation defined. Some SoCs can use 0x00000000-0x0fffffff and
+ 0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff.
+ There might be additional limitations depending on SoCs and the boot mode.
+ The address translation is arbitrary as long as the banks are assigned in
+ the supported address space with the required alignment and they do not
+ overlap one another.
+
+ For example, it is possible to map:
+ bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
+ It is also possible to map:
+ bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
+ There is no reason to stick to a particular translation mapping, but the
+ "ranges" property should provide a "reasonable" default that is known to
+ work. The software should initialize the bus controller according to it.
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+examples:
+ - |
+ // In this example,
+ // - the Ethernet device is connected at the offset 0x01f00000 of CS1 and
+ // mapped to 0x43f00000 of the parent bus.
+ // - the UART device is connected at the offset 0x00200000 of CS5 and
+ // mapped to 0x46200000 of the parent bus.
+
+ system-bus@58c00000 {
+ compatible = "socionext,uniphier-system-bus";
+ reg = <0x58c00000 0x400>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0x00000000 0x42000000 0x02000000>,
+ <5 0x00000000 0x46000000 0x01000000>;
+
+ ethernet@1,01f00000 {
+ compatible = "smsc,lan9115";
+ reg = <1 0x01f00000 0x1000>;
+ interrupts = <0 48 4>;
+ phy-mode = "mii";
+ };
+
+ uart@5,00200000 {
+ compatible = "ns16550a";
+ reg = <5 0x00200000 0x20>;
+ interrupts = <0 49 4>;
+ clock-frequency = <12288000>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/bus/uniphier-system-bus.txt b/Documentation/devicetree/bindings/bus/uniphier-system-bus.txt
deleted file mode 100644
index 68ef80afff16..000000000000
--- a/Documentation/devicetree/bindings/bus/uniphier-system-bus.txt
+++ /dev/null
@@ -1,66 +0,0 @@
-UniPhier System Bus
-
-The UniPhier System Bus is an external bus that connects on-board devices to
-the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
-some control signals. It supports up to 8 banks (chip selects).
-
-Before any access to the bus, the bus controller must be configured; the bus
-controller registers provide the control for the translation from the offset
-within each bank to the CPU-viewed address. The needed setup includes the base
-address, the size of each bank. Optionally, some timing parameters can be
-optimized for faster bus access.
-
-Required properties:
-- compatible: should be "socionext,uniphier-system-bus".
-- reg: offset and length of the register set for the bus controller device.
-- #address-cells: should be 2. The first cell is the bank number (chip select).
- The second cell is the address offset within the bank.
-- #size-cells: should be 1.
-- ranges: should provide a proper address translation from the System Bus to
- the parent bus.
-
-Note:
-The address region(s) that can be assigned for the System Bus is implementation
-defined. Some SoCs can use 0x00000000-0x0fffffff and 0x40000000-0x4fffffff,
-while other SoCs can only use 0x40000000-0x4fffffff. There might be additional
-limitations depending on SoCs and the boot mode. The address translation is
-arbitrary as long as the banks are assigned in the supported address space with
-the required alignment and they do not overlap one another.
-For example, it is possible to map:
- bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
-It is also possible to map:
- bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
-There is no reason to stick to a particular translation mapping, but the
-"ranges" property should provide a "reasonable" default that is known to work.
-The software should initialize the bus controller according to it.
-
-Example:
-
- system-bus {
- compatible = "socionext,uniphier-system-bus";
- reg = <0x58c00000 0x400>;
- #address-cells = <2>;
- #size-cells = <1>;
- ranges = <1 0x00000000 0x42000000 0x02000000
- 5 0x00000000 0x46000000 0x01000000>;
-
- ethernet@1,01f00000 {
- compatible = "smsc,lan9115";
- reg = <1 0x01f00000 0x1000>;
- interrupts = <0 48 4>
- phy-mode = "mii";
- };
-
- uart@5,00200000 {
- compatible = "ns16550a";
- reg = <5 0x00200000 0x20>;
- interrupts = <0 49 4>
- clock-frequency = <12288000>;
- };
- };
-
-In this example,
- - the Ethernet device is connected at the offset 0x01f00000 of CS1 and
- mapped to 0x43f00000 of the parent bus.
- - the UART device is connected at the offset 0x00200000 of CS5 and
- mapped to 0x46200000 of the parent bus.
diff --git a/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml b/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml
new file mode 100644
index 000000000000..6d7396ab8bee
--- /dev/null
+++ b/Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/chrome/google,cros-ec-typec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google Chrome OS EC(Embedded Controller) Type C port driver.
+
+maintainers:
+ - Benson Leung <bleung@chromium.org>
+ - Prashant Malani <pmalani@chromium.org>
+
+description:
+ Chrome OS devices have an Embedded Controller(EC) which has access to
+ Type C port state. This node is intended to allow the host to read and
+ control the Type C ports. The node for this device should be under a
+ cros-ec node like google,cros-ec-spi.
+
+properties:
+ compatible:
+ const: google,cros-ec-typec
+
+ connector:
+ $ref: /schemas/connector/usb-connector.yaml#
+
+required:
+ - compatible
+
+examples:
+ - |+
+ spi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cros_ec: ec@0 {
+ compatible = "google,cros-ec-spi";
+ reg = <0>;
+
+ typec {
+ compatible = "google,cros-ec-typec";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "source";
+ };
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt b/Documentation/devicetree/bindings/clock/clock-bindings.txt
index b646bbcf7f92..8a55fdcf96ee 100644
--- a/Documentation/devicetree/bindings/clock/clock-bindings.txt
+++ b/Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -94,7 +94,7 @@ clock is connected to output 0 of the &ref.
/* external oscillator */
osc: oscillator {
compatible = "fixed-clock";
- #clock-cells = <1>;
+ #clock-cells = <0>;
clock-frequency = <32678>;
clock-output-names = "osc";
};
diff --git a/Documentation/devicetree/bindings/clock/fsl,plldig.yaml b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml
index c8350030b374..a203d5d498db 100644
--- a/Documentation/devicetree/bindings/clock/fsl,plldig.yaml
+++ b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml
@@ -21,6 +21,9 @@ properties:
reg:
maxItems: 1
+ clocks:
+ maxItems: 1
+
'#clock-cells':
const: 0
@@ -41,6 +44,8 @@ required:
- clocks
- '#clock-cells'
+additionalProperties: false
+
examples:
# Display PIXEL Clock node:
- |
diff --git a/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml b/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
index cd0b8a341321..03386b0861a2 100644
--- a/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
@@ -52,6 +52,8 @@ required:
- clock-names
- '#clock-cells'
+additionalProperties: false
+
examples:
# Clock Control Module node:
- |
diff --git a/Documentation/devicetree/bindings/clock/imx8mp-clock.yaml b/Documentation/devicetree/bindings/clock/imx8mp-clock.yaml
index 89aee63c9019..4351a1dbb4f7 100644
--- a/Documentation/devicetree/bindings/clock/imx8mp-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/imx8mp-clock.yaml
@@ -52,6 +52,8 @@ required:
- clock-names
- '#clock-cells'
+additionalProperties: false
+
examples:
# Clock Control Module node:
- |
diff --git a/Documentation/devicetree/bindings/clock/milbeaut-clock.yaml b/Documentation/devicetree/bindings/clock/milbeaut-clock.yaml
index f0b804a7f096..0e8b07710451 100644
--- a/Documentation/devicetree/bindings/clock/milbeaut-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/milbeaut-clock.yaml
@@ -35,6 +35,8 @@ required:
- clocks
- '#clock-cells'
+additionalProperties: false
+
examples:
# Clock controller node:
- |
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
index 3647007f82ca..eacccc88bbf6 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
@@ -68,6 +68,8 @@ required:
- nvmem-cell-names
- '#thermal-sensor-cells'
+additionalProperties: false
+
examples:
- |
clock-controller@900000 {
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml
index 89c6e070e7ac..98572b4a9b60 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml
@@ -40,6 +40,8 @@ required:
- '#clock-cells'
- '#reset-cells'
+additionalProperties: false
+
examples:
- |
clock-controller@1800000 {
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml
index 18e4e77b8cfa..5a5b2214f0ca 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml
@@ -56,6 +56,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
- |
clock-controller@300000 {
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml
index 1d3cae980471..a0bb713929b0 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml
@@ -66,6 +66,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml
index 8cdece395eba..ce06f3f8c3e3 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml
@@ -40,6 +40,8 @@ required:
- '#clock-cells'
- '#reset-cells'
+additionalProperties: false
+
examples:
- |
clock-controller@1800000 {
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
index ee4f968e2909..a345320e0e49 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
@@ -58,6 +58,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
index 888e9a708390..36f3b3668ced 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
@@ -56,6 +56,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
index d18f8ab9eeee..e533bb0cfd2b 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
@@ -74,6 +74,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
# Example for GCC for MSM8960:
- |
diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
index 85518494ce43..f684fe67db84 100644
--- a/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
@@ -74,6 +74,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
if:
properties:
compatible:
diff --git a/Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml
index 7d853c1a85e5..d747bb58f0a7 100644
--- a/Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml
@@ -50,6 +50,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/qcom,gcc-msm8998.h>
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
index 2cd158f13bab..c9fd748b4d7c 100644
--- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
@@ -35,6 +35,8 @@ required:
- compatible
- '#clock-cells'
+additionalProperties: false
+
examples:
# Example for GCC for SDM845: The below node should be defined inside
# &apps_rsc node.
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml
index 0429062f1585..58cdfd5924d3 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml
@@ -58,6 +58,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-gpucc.yaml
index 5785192cc4be..8635e35fd3f0 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc7180-gpucc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-gpucc.yaml
@@ -52,6 +52,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml
index 31df901884ac..0071b9701960 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml
@@ -48,6 +48,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
diff --git a/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml
index 89269ddfbdcd..ad47d747a3e4 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml
@@ -67,6 +67,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
diff --git a/Documentation/devicetree/bindings/clock/qcom,sdm845-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdm845-gpucc.yaml
index bac04f1c5d79..7a052ac5dc00 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sdm845-gpucc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sdm845-gpucc.yaml
@@ -52,6 +52,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
diff --git a/Documentation/devicetree/bindings/clock/qcom,sdm845-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdm845-videocc.yaml
index 9d216c0f11d4..2a6a81ab0318 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sdm845-videocc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sdm845-videocc.yaml
@@ -48,6 +48,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
diff --git a/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml b/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml
new file mode 100644
index 000000000000..c3930edc410f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/socionext,uniphier-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UniPhier clock controller
+
+maintainers:
+ - Masahiro Yamada <yamada.masahiro@socionext.com>
+
+properties:
+ compatible:
+ oneOf:
+ - description: System clock
+ enum:
+ - socionext,uniphier-ld4-clock
+ - socionext,uniphier-pro4-clock
+ - socionext,uniphier-sld8-clock
+ - socionext,uniphier-pro5-clock
+ - socionext,uniphier-pxs2-clock
+ - socionext,uniphier-ld6b-clock
+ - socionext,uniphier-ld11-clock
+ - socionext,uniphier-ld20-clock
+ - socionext,uniphier-pxs3-clock
+ - description: Media I/O (MIO) clock, SD clock
+ enum:
+ - socionext,uniphier-ld4-mio-clock
+ - socionext,uniphier-pro4-mio-clock
+ - socionext,uniphier-sld8-mio-clock
+ - socionext,uniphier-pro5-sd-clock
+ - socionext,uniphier-pxs2-sd-clock
+ - socionext,uniphier-ld11-mio-clock
+ - socionext,uniphier-ld20-sd-clock
+ - socionext,uniphier-pxs3-sd-clock
+ - description: Peripheral clock
+ enum:
+ - socionext,uniphier-ld4-peri-clock
+ - socionext,uniphier-pro4-peri-clock
+ - socionext,uniphier-sld8-peri-clock
+ - socionext,uniphier-pro5-peri-clock
+ - socionext,uniphier-pxs2-peri-clock
+ - socionext,uniphier-ld11-peri-clock
+ - socionext,uniphier-ld20-peri-clock
+ - socionext,uniphier-pxs3-peri-clock
+
+ "#clock-cells":
+ const: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - "#clock-cells"
+
+examples:
+ - |
+ sysctrl@61840000 {
+ compatible = "socionext,uniphier-sysctrl", "simple-mfd", "syscon";
+ reg = <0x61840000 0x4000>;
+
+ clock {
+ compatible = "socionext,uniphier-ld11-clock";
+ #clock-cells = <1>;
+ };
+
+ // other nodes ...
+ };
+
+ - |
+ mioctrl@59810000 {
+ compatible = "socionext,uniphier-mioctrl", "simple-mfd", "syscon";
+ reg = <0x59810000 0x800>;
+
+ clock {
+ compatible = "socionext,uniphier-ld11-mio-clock";
+ #clock-cells = <1>;
+ };
+
+ // other nodes ...
+ };
+
+ - |
+ perictrl@59820000 {
+ compatible = "socionext,uniphier-perictrl", "simple-mfd", "syscon";
+ reg = <0x59820000 0x200>;
+
+ clock {
+ compatible = "socionext,uniphier-ld11-peri-clock";
+ #clock-cells = <1>;
+ };
+
+ // other nodes ...
+ };
diff --git a/Documentation/devicetree/bindings/clock/uniphier-clock.txt b/Documentation/devicetree/bindings/clock/uniphier-clock.txt
deleted file mode 100644
index 7b5f602765fe..000000000000
--- a/Documentation/devicetree/bindings/clock/uniphier-clock.txt
+++ /dev/null
@@ -1,132 +0,0 @@
-UniPhier clock controller
-
-
-System clock
-------------
-
-Required properties:
-- compatible: should be one of the following:
- "socionext,uniphier-ld4-clock" - for LD4 SoC.
- "socionext,uniphier-pro4-clock" - for Pro4 SoC.
- "socionext,uniphier-sld8-clock" - for sLD8 SoC.
- "socionext,uniphier-pro5-clock" - for Pro5 SoC.
- "socionext,uniphier-pxs2-clock" - for PXs2/LD6b SoC.
- "socionext,uniphier-ld11-clock" - for LD11 SoC.
- "socionext,uniphier-ld20-clock" - for LD20 SoC.
- "socionext,uniphier-pxs3-clock" - for PXs3 SoC
-- #clock-cells: should be 1.
-
-Example:
-
- sysctrl@61840000 {
- compatible = "socionext,uniphier-sysctrl",
- "simple-mfd", "syscon";
- reg = <0x61840000 0x4000>;
-
- clock {
- compatible = "socionext,uniphier-ld11-clock";
- #clock-cells = <1>;
- };
-
- other nodes ...
- };
-
-Provided clocks:
-
- 8: ST DMAC
-12: GIO (Giga bit stream I/O)
-14: USB3 ch0 host
-15: USB3 ch1 host
-16: USB3 ch0 PHY0
-17: USB3 ch0 PHY1
-20: USB3 ch1 PHY0
-21: USB3 ch1 PHY1
-
-
-Media I/O (MIO) clock, SD clock
--------------------------------
-
-Required properties:
-- compatible: should be one of the following:
- "socionext,uniphier-ld4-mio-clock" - for LD4 SoC.
- "socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.
- "socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.
- "socionext,uniphier-pro5-sd-clock" - for Pro5 SoC.
- "socionext,uniphier-pxs2-sd-clock" - for PXs2/LD6b SoC.
- "socionext,uniphier-ld11-mio-clock" - for LD11 SoC.
- "socionext,uniphier-ld20-sd-clock" - for LD20 SoC.
- "socionext,uniphier-pxs3-sd-clock" - for PXs3 SoC
-- #clock-cells: should be 1.
-
-Example:
-
- mioctrl@59810000 {
- compatible = "socionext,uniphier-mioctrl",
- "simple-mfd", "syscon";
- reg = <0x59810000 0x800>;
-
- clock {
- compatible = "socionext,uniphier-ld11-mio-clock";
- #clock-cells = <1>;
- };
-
- other nodes ...
- };
-
-Provided clocks:
-
- 0: SD ch0 host
- 1: eMMC host
- 2: SD ch1 host
- 7: MIO DMAC
- 8: USB2 ch0 host
- 9: USB2 ch1 host
-10: USB2 ch2 host
-12: USB2 ch0 PHY
-13: USB2 ch1 PHY
-14: USB2 ch2 PHY
-
-
-Peripheral clock
-----------------
-
-Required properties:
-- compatible: should be one of the following:
- "socionext,uniphier-ld4-peri-clock" - for LD4 SoC.
- "socionext,uniphier-pro4-peri-clock" - for Pro4 SoC.
- "socionext,uniphier-sld8-peri-clock" - for sLD8 SoC.
- "socionext,uniphier-pro5-peri-clock" - for Pro5 SoC.
- "socionext,uniphier-pxs2-peri-clock" - for PXs2/LD6b SoC.
- "socionext,uniphier-ld11-peri-clock" - for LD11 SoC.
- "socionext,uniphier-ld20-peri-clock" - for LD20 SoC.
- "socionext,uniphier-pxs3-peri-clock" - for PXs3 SoC
-- #clock-cells: should be 1.
-
-Example:
-
- perictrl@59820000 {
- compatible = "socionext,uniphier-perictrl",
- "simple-mfd", "syscon";
- reg = <0x59820000 0x200>;
-
- clock {
- compatible = "socionext,uniphier-ld11-peri-clock";
- #clock-cells = <1>;
- };
-
- other nodes ...
- };
-
-Provided clocks:
-
- 0: UART ch0
- 1: UART ch1
- 2: UART ch2
- 3: UART ch3
- 4: I2C ch0
- 5: I2C ch1
- 6: I2C ch2
- 7: I2C ch3
- 8: I2C ch4
- 9: I2C ch5
-10: I2C ch6
diff --git a/Documentation/devicetree/bindings/connector/samsung,usb-connector-11pin.txt b/Documentation/devicetree/bindings/connector/samsung,usb-connector-11pin.txt
index 22256e295a7a..3dd8961154ab 100644
--- a/Documentation/devicetree/bindings/connector/samsung,usb-connector-11pin.txt
+++ b/Documentation/devicetree/bindings/connector/samsung,usb-connector-11pin.txt
@@ -19,7 +19,7 @@ Required nodes:
0: High Speed (HS),
3: Mobile High-Definition Link (MHL), specific to 11-pin Samsung micro-USB.
-[1]: bindings/connector/usb-connector.txt
+[1]: bindings/connector/usb-connector.yaml
Example
-------
diff --git a/Documentation/devicetree/bindings/connector/usb-connector.txt b/Documentation/devicetree/bindings/connector/usb-connector.txt
deleted file mode 100644
index 88578ac1a8a7..000000000000
--- a/Documentation/devicetree/bindings/connector/usb-connector.txt
+++ /dev/null
@@ -1,135 +0,0 @@
-USB Connector
-=============
-
-A USB connector node represents a physical USB connector. It should be
-a child of a USB interface controller.
-
-Required properties:
-- compatible: describes type of the connector, must be one of:
- "usb-a-connector",
- "usb-b-connector",
- "usb-c-connector".
-
-Optional properties:
-- label: symbolic name for the connector,
-- type: size of the connector, should be specified in case of USB-A, USB-B
- non-fullsize connectors: "mini", "micro".
-- self-powered: Set this property if the usb device that has its own power
- source.
-
-Optional properties for usb-b-connector:
-- id-gpios: an input gpio for USB ID pin.
-- vbus-gpios: an input gpio for USB VBUS pin, used to detect presence of
- VBUS 5V.
- see gpio/gpio.txt.
-- vbus-supply: a phandle to the regulator for USB VBUS if needed when host
- mode or dual role mode is supported.
- Particularly, if use an output GPIO to control a VBUS regulator, should
- model it as a regulator.
- see regulator/fixed-regulator.yaml
-- pinctrl-names : a pinctrl state named "default" is optional
-- pinctrl-0 : pin control group
- see pinctrl/pinctrl-bindings.txt
-
-Optional properties for usb-c-connector:
-- power-role: should be one of "source", "sink" or "dual"(DRP) if typec
- connector has power support.
-- try-power-role: preferred power role if "dual"(DRP) can support Try.SNK
- or Try.SRC, should be "sink" for Try.SNK or "source" for Try.SRC.
-- data-role: should be one of "host", "device", "dual"(DRD) if typec
- connector supports USB data.
-
-Required properties for usb-c-connector with power delivery support:
-- source-pdos: An array of u32 with each entry providing supported power
- source data object(PDO), the detailed bit definitions of PDO can be found
- in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.2
- Source_Capabilities Message, the order of each entry(PDO) should follow
- the PD spec chapter 6.4.1. Required for power source and power dual role.
- User can specify the source PDO array via PDO_FIXED/BATT/VAR/PPS_APDO()
- defined in dt-bindings/usb/pd.h.
-- sink-pdos: An array of u32 with each entry providing supported power
- sink data object(PDO), the detailed bit definitions of PDO can be found
- in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.3
- Sink Capabilities Message, the order of each entry(PDO) should follow
- the PD spec chapter 6.4.1. Required for power sink and power dual role.
- User can specify the sink PDO array via PDO_FIXED/BATT/VAR/PPS_APDO() defined
- in dt-bindings/usb/pd.h.
-- op-sink-microwatt: Sink required operating power in microwatt, if source
- can't offer the power, Capability Mismatch is set. Required for power
- sink and power dual role.
-
-Required nodes:
-- any data bus to the connector should be modeled using the OF graph bindings
- specified in bindings/graph.txt, unless the bus is between parent node and
- the connector. Since single connector can have multiple data buses every bus
- has assigned OF graph port number as follows:
- 0: High Speed (HS), present in all connectors,
- 1: Super Speed (SS), present in SS capable connectors,
- 2: Sideband use (SBU), present in USB-C.
-
-Examples
---------
-
-1. Micro-USB connector with HS lines routed via controller (MUIC):
-
-muic-max77843@66 {
- ...
- usb_con: connector {
- compatible = "usb-b-connector";
- label = "micro-USB";
- type = "micro";
- };
-};
-
-2. USB-C connector attached to CC controller (s2mm005), HS lines routed
-to companion PMIC (max77865), SS lines to USB3 PHY and SBU to DisplayPort.
-DisplayPort video lines are routed to the connector via SS mux in USB3 PHY.
-
-ccic: s2mm005@33 {
- ...
- usb_con: connector {
- compatible = "usb-c-connector";
- label = "USB-C";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- usb_con_hs: endpoint {
- remote-endpoint = <&max77865_usbc_hs>;
- };
- };
- port@1 {
- reg = <1>;
- usb_con_ss: endpoint {
- remote-endpoint = <&usbdrd_phy_ss>;
- };
- };
- port@2 {
- reg = <2>;
- usb_con_sbu: endpoint {
- remote-endpoint = <&dp_aux>;
- };
- };
- };
- };
-};
-
-3. USB-C connector attached to a typec port controller(ptn5110), which has
-power delivery support and enables drp.
-
-typec: ptn5110@50 {
- ...
- usb_con: connector {
- compatible = "usb-c-connector";
- label = "USB-C";
- power-role = "dual";
- try-power-role = "sink";
- source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
- sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)
- PDO_VAR(5000, 12000, 2000)>;
- op-sink-microwatt = <10000000>;
- };
-};
diff --git a/Documentation/devicetree/bindings/connector/usb-connector.yaml b/Documentation/devicetree/bindings/connector/usb-connector.yaml
new file mode 100644
index 000000000000..4638d7adb806
--- /dev/null
+++ b/Documentation/devicetree/bindings/connector/usb-connector.yaml
@@ -0,0 +1,206 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/connector/usb-connector.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: USB Connector
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+
+description:
+ A USB connector node represents a physical USB connector. It should be a child
+ of a USB interface controller.
+
+properties:
+ compatible:
+ enum:
+ - usb-a-connector
+ - usb-b-connector
+ - usb-c-connector
+
+ label:
+ description: Symbolic name for the connector.
+
+ type:
+ description: Size of the connector, should be specified in case of
+ non-fullsize 'usb-a-connector' or 'usb-b-connector' compatible
+ connectors.
+ allOf:
+ - $ref: /schemas/types.yaml#definitions/string
+ enum:
+ - mini
+ - micro
+
+ self-powered:
+ description: Set this property if the USB device has its own power source.
+ type: boolean
+
+ # The following are optional properties for "usb-b-connector".
+ id-gpios:
+ description: An input gpio for USB ID pin.
+ maxItems: 1
+
+ vbus-gpios:
+ description: An input gpio for USB VBus pin, used to detect presence of
+ VBUS 5V.
+ maxItems: 1
+
+ vbus-supply:
+ description: A phandle to the regulator for USB VBUS if needed when host
+ mode or dual role mode is supported.
+ Particularly, if use an output GPIO to control a VBUS regulator, should
+ model it as a regulator. See bindings/regulator/fixed-regulator.yaml
+
+ # The following are optional properties for "usb-c-connector".
+ power-role:
+ description: Determines the power role that the Type C connector will
+ support. "dual" refers to Dual Role Port (DRP).
+ allOf:
+ - $ref: /schemas/types.yaml#definitions/string
+ enum:
+ - source
+ - sink
+ - dual
+
+ try-power-role:
+ description: Preferred power role.
+ allOf:
+ - $ref: /schemas/types.yaml#definitions/string
+ enum:
+ - source
+ - sink
+ - dual
+
+ data-role:
+ description: Data role if Type C connector supports USB data. "dual" refers
+ Dual Role Device (DRD).
+ allOf:
+ - $ref: /schemas/types.yaml#definitions/string
+ enum:
+ - host
+ - device
+ - dual
+
+ # The following are optional properties for "usb-c-connector" with power
+ # delivery support.
+ source-pdos:
+ description: An array of u32 with each entry providing supported power
+ source data object(PDO), the detailed bit definitions of PDO can be found
+ in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.2
+ Source_Capabilities Message, the order of each entry(PDO) should follow
+ the PD spec chapter 6.4.1. Required for power source and power dual role.
+ User can specify the source PDO array via PDO_FIXED/BATT/VAR/PPS_APDO()
+ defined in dt-bindings/usb/pd.h.
+ minItems: 1
+ maxItems: 7
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+
+ sink-pdos:
+ description: An array of u32 with each entry providing supported power sink
+ data object(PDO), the detailed bit definitions of PDO can be found in
+ "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.3
+ Sink Capabilities Message, the order of each entry(PDO) should follow the
+ PD spec chapter 6.4.1. Required for power sink and power dual role. User
+ can specify the sink PDO array via PDO_FIXED/BATT/VAR/PPS_APDO() defined
+ in dt-bindings/usb/pd.h.
+ minItems: 1
+ maxItems: 7
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+
+ op-sink-microwatt:
+ description: Sink required operating power in microwatt, if source can't
+ offer the power, Capability Mismatch is set. Required for power sink and
+ power dual role.
+
+ ports:
+ description: OF graph bindings (specified in bindings/graph.txt) that model
+ any data bus to the connector unless the bus is between parent node and
+ the connector. Since a single connector can have multiple data buses every
+ bus has an assigned OF graph port number as described below.
+ type: object
+ properties:
+ port@0:
+ type: object
+ description: High Speed (HS), present in all connectors.
+
+ port@1:
+ type: object
+ description: Super Speed (SS), present in SS capable connectors.
+
+ port@2:
+ type: object
+ description: Sideband Use (SBU), present in USB-C. This describes the
+ alternate mode connection of which SBU is a part.
+
+ required:
+ - port@0
+
+required:
+ - compatible
+
+examples:
+ # Micro-USB connector with HS lines routed via controller (MUIC).
+ - |+
+ muic-max77843 {
+ usb_con1: connector {
+ compatible = "usb-b-connector";
+ label = "micro-USB";
+ type = "micro";
+ };
+ };
+
+ # USB-C connector attached to CC controller (s2mm005), HS lines routed
+ # to companion PMIC (max77865), SS lines to USB3 PHY and SBU to DisplayPort.
+ # DisplayPort video lines are routed to the connector via SS mux in USB3 PHY.
+ - |+
+ ccic: s2mm005 {
+ usb_con2: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ usb_con_hs: endpoint {
+ remote-endpoint = <&max77865_usbc_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ usb_con_ss: endpoint {
+ remote-endpoint = <&usbdrd_phy_ss>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+ usb_con_sbu: endpoint {
+ remote-endpoint = <&dp_aux>;
+ };
+ };
+ };
+ };
+ };
+
+ # USB-C connector attached to a typec port controller(ptn5110), which has
+ # power delivery support and enables drp.
+ - |+
+ #include <dt-bindings/usb/pd.h>
+ typec: ptn5110 {
+ usb_con3: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 12000, 2000)>;
+ op-sink-microwatt = <10000000>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
index d1205a6697a0..a8d202c9d004 100644
--- a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
+++ b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
@@ -71,9 +71,9 @@ properties:
maxItems: 2
reg-names:
- items:
- - const: vpu
- - const: hhi
+ items:
+ - const: vpu
+ - const: hhi
interrupts:
maxItems: 1
@@ -107,6 +107,8 @@ required:
- "#address-cells"
- "#size-cells"
+additionalProperties: false
+
examples:
- |
vpu: vpu@d0100000 {
diff --git a/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt b/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt
deleted file mode 100644
index 8def11b16a24..000000000000
--- a/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-Vivante GPU core devices
-========================
-
-Required properties:
-- compatible: Should be "vivante,gc"
- A more specific compatible is not needed, as the cores contain chip
- identification registers at fixed locations, which provide all the
- necessary information to the driver.
-- reg: should be register base and length as documented in the
- datasheet
-- interrupts: Should contain the cores interrupt line
-- clocks: should contain one clock for entry in clock-names
- see Documentation/devicetree/bindings/clock/clock-bindings.txt
-- clock-names:
- - "bus": AXI/master interface clock
- - "reg": AHB/slave interface clock
- (only required if GPU can gate slave interface independently)
- - "core": GPU core clock
- - "shader": Shader clock (only required if GPU has feature PIPE_3D)
-
-Optional properties:
-- power-domains: a power domain consumer specifier according to
- Documentation/devicetree/bindings/power/power_domain.txt
-
-example:
-
-gpu_3d: gpu@130000 {
- compatible = "vivante,gc";
- reg = <0x00130000 0x4000>;
- interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
- <&clks IMX6QDL_CLK_GPU3D_CORE>,
- <&clks IMX6QDL_CLK_GPU3D_SHADER>;
- clock-names = "bus", "core", "shader";
- power-domains = <&gpc 1>;
-};
diff --git a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml
index 2ca3ddbe1ff4..e7f2ad7dab5e 100644
--- a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml
+++ b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml
@@ -43,6 +43,8 @@ required:
- interrupts
- '#dma-cells'
+additionalProperties: false
+
examples:
- |
dma@3000000 {
diff --git a/Documentation/devicetree/bindings/dma/socionext,uniphier-mio-dmac.yaml b/Documentation/devicetree/bindings/dma/socionext,uniphier-mio-dmac.yaml
new file mode 100644
index 000000000000..e7bf6dd7da29
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/socionext,uniphier-mio-dmac.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/socionext,uniphier-mio-dmac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UniPhier Media IO DMA controller
+
+description: |
+ This works as an external DMA engine for SD/eMMC controllers etc.
+ found in UniPhier LD4, Pro4, sLD8 SoCs.
+
+maintainers:
+ - Masahiro Yamada <yamada.masahiro@socionext.com>
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ compatible:
+ const: socionext,uniphier-mio-dmac
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: |
+ A list of interrupt specifiers associated with the DMA channels.
+ The number of interrupt lines is SoC-dependent.
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ '#dma-cells':
+ description: The single cell represents the channel index.
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - '#dma-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ // In the example below, "interrupts = <0 68 4>, <0 68 4>, ..." is not a
+ // typo. The first two channels share a single interrupt line.
+
+ dmac: dma-controller@5a000000 {
+ compatible = "socionext,uniphier-mio-dmac";
+ reg = <0x5a000000 0x1000>;
+ interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
+ <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
+ clocks = <&mio_clk 7>;
+ resets = <&mio_rst 7>;
+ #dma-cells = <1>;
+ };
diff --git a/Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt b/Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt
deleted file mode 100644
index b12388dc7eac..000000000000
--- a/Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-UniPhier Media IO DMA controller
-
-This works as an external DMA engine for SD/eMMC controllers etc.
-found in UniPhier LD4, Pro4, sLD8 SoCs.
-
-Required properties:
-- compatible: should be "socionext,uniphier-mio-dmac".
-- reg: offset and length of the register set for the device.
-- interrupts: a list of interrupt specifiers associated with the DMA channels.
-- clocks: a single clock specifier.
-- #dma-cells: should be <1>. The single cell represents the channel index.
-
-Example:
- dmac: dma-controller@5a000000 {
- compatible = "socionext,uniphier-mio-dmac";
- reg = <0x5a000000 0x1000>;
- interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
- <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
- clocks = <&mio_clk 7>;
- #dma-cells = <1>;
- };
-
-Note:
-In the example above, "interrupts = <0 68 4>, <0 68 4>, ..." is not a typo.
-The first two channels share a single interrupt line.
diff --git a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
index f04870d84542..a5dc070d0ca7 100644
--- a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
+++ b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
@@ -68,6 +68,8 @@ required:
- mbox-names
- memory-region
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/firmware/imx/rsrc.h>
diff --git a/Documentation/devicetree/bindings/eeprom/at24.yaml b/Documentation/devicetree/bindings/eeprom/at24.yaml
index 0f6d8db18d6c..a15787e504f0 100644
--- a/Documentation/devicetree/bindings/eeprom/at24.yaml
+++ b/Documentation/devicetree/bindings/eeprom/at24.yaml
@@ -172,6 +172,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
i2c {
diff --git a/Documentation/devicetree/bindings/example-schema.yaml b/Documentation/devicetree/bindings/example-schema.yaml
index 4ddcf709cc3c..62811a1b5058 100644
--- a/Documentation/devicetree/bindings/example-schema.yaml
+++ b/Documentation/devicetree/bindings/example-schema.yaml
@@ -7,9 +7,9 @@
# $id is a unique identifier based on the filename. There may or may not be a
# file present at the URL.
-$id: "http://devicetree.org/schemas/example-schema.yaml#"
+$id: http://devicetree.org/schemas/example-schema.yaml#
# $schema is the meta-schema this schema should be validated with.
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: An example schema annotated with jsonschema details
diff --git a/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml b/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
index 878a2079ebb6..1bd2870c3a9c 100644
--- a/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
+++ b/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
@@ -34,9 +34,12 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
npe@c8006000 {
compatible = "intel,ixp4xx-network-processing-engine";
reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
};
+...
diff --git a/Documentation/devicetree/bindings/gnss/gnss.txt b/Documentation/devicetree/bindings/gnss/gnss.txt
index f547bd4549fe..d6dc9c0d8249 100644
--- a/Documentation/devicetree/bindings/gnss/gnss.txt
+++ b/Documentation/devicetree/bindings/gnss/gnss.txt
@@ -8,7 +8,7 @@ bus (e.g. UART, I2C or SPI).
Please refer to the following documents for generic properties:
- Documentation/devicetree/bindings/serial/slave-device.txt
+ Documentation/devicetree/bindings/serial/serial.yaml
Documentation/devicetree/bindings/spi/spi-bus.txt
Required properties:
diff --git a/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml b/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml
index 64e279a4bc10..5f1ed20e43ee 100644
--- a/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc-gpio.yaml
@@ -47,6 +47,8 @@ required:
- "#gpio-cells"
- gpio-controller
+additionalProperties: false
+
dependencies:
interrupt-controller: [ interrupts ]
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
index 2e097b57f170..0fc6700ed800 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
@@ -14,7 +14,7 @@ Required properties:
"marvell,armada-8k-gpio" should be used for the Armada 7K and 8K
SoCs (either from AP or CP), see
- Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
+ Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt
for specific details about the offset property.
- reg: Address and length of the register set for the device. Only one
diff --git a/Documentation/devicetree/bindings/gpio/gpio-uniphier.txt b/Documentation/devicetree/bindings/gpio/gpio-uniphier.txt
deleted file mode 100644
index f281f12dac18..000000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-uniphier.txt
+++ /dev/null
@@ -1,51 +0,0 @@
-UniPhier GPIO controller
-
-Required properties:
-- compatible: Should be "socionext,uniphier-gpio".
-- reg: Specifies offset and length of the register set for the device.
-- gpio-controller: Marks the device node as a GPIO controller.
-- #gpio-cells: Should be 2. The first cell is the pin number and the second
- cell is used to specify optional parameters.
-- interrupt-controller: Marks the device node as an interrupt controller.
-- #interrupt-cells: Should be 2. The first cell defines the interrupt number.
- The second cell bits[3:0] is used to specify trigger type as follows:
- 1 = low-to-high edge triggered
- 2 = high-to-low edge triggered
- 4 = active high level-sensitive
- 8 = active low level-sensitive
- Valid combinations are 1, 2, 3, 4, 8.
-- ngpios: Specifies the number of GPIO lines.
-- gpio-ranges: Mapping to pin controller pins (as described in gpio.txt)
-- socionext,interrupt-ranges: Specifies an interrupt number mapping between
- this GPIO controller and its interrupt parent, in the form of arbitrary
- number of <child-interrupt-base parent-interrupt-base length> triplets.
-
-Optional properties:
-- gpio-ranges-group-names: Used for named gpio ranges (as described in gpio.txt)
-
-Example:
- gpio: gpio@55000000 {
- compatible = "socionext,uniphier-gpio";
- reg = <0x55000000 0x200>;
- interrupt-parent = <&aidet>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 0 0>;
- gpio-ranges-group-names = "gpio_range";
- ngpios = <248>;
- socionext,interrupt-ranges = <0 48 16>, <16 154 5>, <21 217 3>;
- };
-
-Consumer Example:
-
- sdhci0_pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio UNIPHIER_GPIO_PORT(29, 4) GPIO_ACTIVE_LOW>;
- };
-
-Please note UNIPHIER_GPIO_PORT(29, 4) represents PORT294 in the SoC document.
-Unfortunately, only the one's place is octal in the port numbering. (That is,
-PORT 8, 9, 18, 19, 28, 29, ... are missing.) UNIPHIER_GPIO_PORT() is a helper
-macro to calculate 29 * 8 + 4.
diff --git a/Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml b/Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml
new file mode 100644
index 000000000000..c58ff9a94f45
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UniPhier GPIO controller
+
+maintainers:
+ - Masahiro Yamada <yamada.masahiro@socionext.com>
+
+properties:
+ $nodename:
+ pattern: "^gpio@[0-9a-f]+$"
+
+ compatible:
+ const: socionext,uniphier-gpio
+
+ reg:
+ maxItems: 1
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ description: |
+ The first cell defines the interrupt number.
+ The second cell bits[3:0] is used to specify trigger type as follows:
+ 1 = low-to-high edge triggered
+ 2 = high-to-low edge triggered
+ 4 = active high level-sensitive
+ 8 = active low level-sensitive
+ Valid combinations are 1, 2, 3, 4, 8.
+ const: 2
+
+ ngpios:
+ minimum: 0
+ maximum: 512
+
+ gpio-ranges: true
+
+ gpio-ranges-group-names:
+ $ref: /schemas/types.yaml#/definitions/string-array
+
+ socionext,interrupt-ranges:
+ description: |
+ Specifies an interrupt number mapping between this GPIO controller and
+ its interrupt parent, in the form of arbitrary number of
+ <child-interrupt-base parent-interrupt-base length> triplets.
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - "#gpio-cells"
+ - interrupt-controller
+ - "#interrupt-cells"
+ - ngpios
+ - gpio-ranges
+ - socionext,interrupt-ranges
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/gpio/uniphier-gpio.h>
+
+ gpio: gpio@55000000 {
+ compatible = "socionext,uniphier-gpio";
+ reg = <0x55000000 0x200>;
+ interrupt-parent = <&aidet>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 0>;
+ gpio-ranges-group-names = "gpio_range";
+ ngpios = <248>;
+ socionext,interrupt-ranges = <0 48 16>, <16 154 5>, <21 217 3>;
+ };
+
+ // Consumer:
+ // Please note UNIPHIER_GPIO_PORT(29, 4) represents PORT294 in the SoC
+ // document. Unfortunately, only the one's place is octal in the port
+ // numbering. (That is, PORT 8, 9, 18, 19, 28, 29, ... do not exist.)
+ // UNIPHIER_GPIO_PORT() is a helper macro to calculate 29 * 8 + 4.
+ sdhci0_pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio UNIPHIER_GPIO_PORT(29, 4) GPIO_ACTIVE_LOW>;
+ };
diff --git a/Documentation/devicetree/bindings/gpio/xylon,logicvc-gpio.yaml b/Documentation/devicetree/bindings/gpio/xylon,logicvc-gpio.yaml
index d102888c1be7..a36aec27069c 100644
--- a/Documentation/devicetree/bindings/gpio/xylon,logicvc-gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/xylon,logicvc-gpio.yaml
@@ -49,6 +49,8 @@ required:
- "#gpio-cells"
- gpio-controller
+additionalProperties: false
+
examples:
- |
logicvc: logicvc@43c00000 {
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
index e8b99adcb1bd..0b229a7d4a98 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
@@ -43,6 +43,9 @@ properties:
operating-points-v2: true
+ resets:
+ maxItems: 2
+
required:
- compatible
- reg
@@ -50,6 +53,8 @@ required:
- interrupt-names
- clocks
+additionalProperties: false
+
allOf:
- if:
properties:
@@ -57,9 +62,6 @@ allOf:
contains:
const: amlogic,meson-g12a-mali
then:
- properties:
- resets:
- minItems: 2
required:
- resets
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml
index 8d966f3ff3db..0407e45eb8c4 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml
@@ -75,6 +75,9 @@ properties:
mali-supply: true
+ power-domains:
+ maxItems: 1
+
resets:
minItems: 1
maxItems: 2
@@ -91,6 +94,8 @@ required:
- interrupt-names
- clocks
+additionalProperties: false
+
allOf:
- if:
properties:
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml
index afde81be3c29..f5401cc8de4a 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml
@@ -115,6 +115,8 @@ required:
- clocks
- clock-names
+additionalProperties: false
+
allOf:
- if:
properties:
diff --git a/Documentation/devicetree/bindings/gpu/samsung-rotator.yaml b/Documentation/devicetree/bindings/gpu/samsung-rotator.yaml
index f4dfa6fc724c..665c6e3b31d3 100644
--- a/Documentation/devicetree/bindings/gpu/samsung-rotator.yaml
+++ b/Documentation/devicetree/bindings/gpu/samsung-rotator.yaml
@@ -36,6 +36,8 @@ required:
- clocks
- clock-names
+additionalProperties: false
+
examples:
- |
rotator@12810000 {
diff --git a/Documentation/devicetree/bindings/gpu/vivante,gc.yaml b/Documentation/devicetree/bindings/gpu/vivante,gc.yaml
new file mode 100644
index 000000000000..0bc4b38d5cbb
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/vivante,gc.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/vivante,gc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Vivante GPU Bindings
+
+description: Vivante GPU core devices
+
+maintainers:
+ - Lucas Stach <l.stach@pengutronix.de>
+
+properties:
+ compatible:
+ const: vivante,gc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: AXI/master interface clock
+ - description: GPU core clock
+ - description: Shader clock (only required if GPU has feature PIPE_3D)
+ - description: AHB/slave interface clock (only required if GPU can gate slave interface independently)
+ minItems: 1
+ maxItems: 4
+
+ clock-names:
+ items:
+ enum: [ bus, core, shader, reg ]
+ minItems: 1
+ maxItems: 4
+
+ resets:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx6qdl-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ gpu@130000 {
+ compatible = "vivante,gc";
+ reg = <0x00130000 0x4000>;
+ interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
+ <&clks IMX6QDL_CLK_GPU3D_CORE>,
+ <&clks IMX6QDL_CLK_GPU3D_SHADER>;
+ clock-names = "bus", "core", "shader";
+ power-domains = <&gpc 1>;
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml b/Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml
index 2a9822075b36..154bee851139 100644
--- a/Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml
+++ b/Documentation/devicetree/bindings/hwmon/adi,adm1177.yaml
@@ -47,6 +47,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/gpio/gpio.h>
diff --git a/Documentation/devicetree/bindings/hwmon/adi,ltc2947.yaml b/Documentation/devicetree/bindings/hwmon/adi,ltc2947.yaml
index 6a742a51e2f9..44a63fffb4be 100644
--- a/Documentation/devicetree/bindings/hwmon/adi,ltc2947.yaml
+++ b/Documentation/devicetree/bindings/hwmon/adi,ltc2947.yaml
@@ -87,6 +87,8 @@ required:
- reg
+additionalProperties: false
+
examples:
- |
spi {
diff --git a/Documentation/devicetree/bindings/hwmon/pmbus/ti,ucd90320.yaml b/Documentation/devicetree/bindings/hwmon/pmbus/ti,ucd90320.yaml
index 5d42e1304202..e8feee38c76c 100644
--- a/Documentation/devicetree/bindings/hwmon/pmbus/ti,ucd90320.yaml
+++ b/Documentation/devicetree/bindings/hwmon/pmbus/ti,ucd90320.yaml
@@ -32,6 +32,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
i2c {
diff --git a/Documentation/devicetree/bindings/hwmon/ti,tmp513.yaml b/Documentation/devicetree/bindings/hwmon/ti,tmp513.yaml
index 168235ad5d81..3f043e943668 100644
--- a/Documentation/devicetree/bindings/hwmon/ti,tmp513.yaml
+++ b/Documentation/devicetree/bindings/hwmon/ti,tmp513.yaml
@@ -76,6 +76,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
i2c {
diff --git a/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt b/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt
deleted file mode 100644
index 22f2eeb2c4c9..000000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-rk3x.txt
+++ /dev/null
@@ -1,68 +0,0 @@
-* Rockchip RK3xxx I2C controller
-
-This driver interfaces with the native I2C controller present in Rockchip
-RK3xxx SoCs.
-
-Required properties :
-
- - reg : Offset and length of the register set for the device
- - compatible: should be one of the following:
- - "rockchip,rv1108-i2c": for rv1108
- - "rockchip,rk3066-i2c": for rk3066
- - "rockchip,rk3188-i2c": for rk3188
- - "rockchip,rk3228-i2c": for rk3228
- - "rockchip,rk3288-i2c": for rk3288
- - "rockchip,rk3328-i2c", "rockchip,rk3399-i2c": for rk3328
- - "rockchip,rk3399-i2c": for rk3399
- - interrupts : interrupt number
- - clocks: See ../clock/clock-bindings.txt
- - For older hardware (rk3066, rk3188, rk3228, rk3288):
- - There is one clock that's used both to derive the functional clock
- for the device and as the bus clock.
- - For newer hardware (rk3399): specified by name
- - "i2c": This is used to derive the functional clock.
- - "pclk": This is the bus clock.
-
-Required on RK3066, RK3188 :
-
- - rockchip,grf : the phandle of the syscon node for the general register
- file (GRF)
- - on those SoCs an alias with the correct I2C bus ID (bit offset in the GRF)
- is also required.
-
-Optional properties :
-
- - clock-frequency : SCL frequency to use (in Hz). If omitted, 100kHz is used.
- - i2c-scl-rising-time-ns : Number of nanoseconds the SCL signal takes to rise
- (t(r) in I2C specification). If not specified this is assumed to be
- the maximum the specification allows(1000 ns for Standard-mode,
- 300 ns for Fast-mode) which might cause slightly slower communication.
- - i2c-scl-falling-time-ns : Number of nanoseconds the SCL signal takes to fall
- (t(f) in the I2C specification). If not specified this is assumed to
- be the maximum the specification allows (300 ns) which might cause
- slightly slower communication.
- - i2c-sda-falling-time-ns : Number of nanoseconds the SDA signal takes to fall
- (t(f) in the I2C specification). If not specified we'll use the SCL
- value since they are the same in nearly all cases.
-
-Example:
-
-aliases {
- i2c0 = &i2c0;
-}
-
-i2c0: i2c@2002d000 {
- compatible = "rockchip,rk3188-i2c";
- reg = <0x2002d000 0x1000>;
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- rockchip,grf = <&grf>;
-
- clock-names = "i2c";
- clocks = <&cru PCLK_I2C0>;
-
- i2c-scl-rising-time-ns = <800>;
- i2c-scl-falling-time-ns = <100>;
-};
diff --git a/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml b/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
new file mode 100644
index 000000000000..61eac76c84c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
@@ -0,0 +1,136 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/i2c-rk3x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3xxx I2C controller
+
+description:
+ This driver interfaces with the native I2C controller present in Rockchip
+ RK3xxx SoCs.
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+# Everything else is described in the common file
+properties:
+ compatible:
+ oneOf:
+ - const: rockchip,rv1108-i2c
+ - const: rockchip,rk3066-i2c
+ - const: rockchip,rk3188-i2c
+ - const: rockchip,rk3228-i2c
+ - const: rockchip,rk3288-i2c
+ - const: rockchip,rk3399-i2c
+ - items:
+ - enum:
+ - rockchip,rk3036-i2c
+ - rockchip,rk3368-i2c
+ - const: rockchip,rk3288-i2c
+ - items:
+ - enum:
+ - rockchip,px30-i2c
+ - rockchip,rk3308-i2c
+ - rockchip,rk3328-i2c
+ - const: rockchip,rk3399-i2c
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ items:
+ - description:
+ For older hardware (rk3066, rk3188, rk3228, rk3288)
+ there is one clock that is used both to derive the functional clock
+ for the device and as the bus clock.
+ For newer hardware (rk3399) this clock is used to derive
+ the functional clock
+ - description:
+ For newer hardware (rk3399) this is the bus clock
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: i2c
+ - const: pclk
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Required on RK3066, RK3188 the phandle of the syscon node for
+ the general register file (GRF)
+ On those SoCs an alias with the correct I2C bus ID
+ (bit offset in the GRF) is also required.
+
+ clock-frequency:
+ default: 100000
+ description:
+ SCL frequency to use (in Hz). If omitted, 100kHz is used.
+
+ i2c-scl-rising-time-ns:
+ default: 1000
+ description:
+ Number of nanoseconds the SCL signal takes to rise
+ (t(r) in I2C specification). If not specified this is assumed to be
+ the maximum the specification allows(1000 ns for Standard-mode,
+ 300 ns for Fast-mode) which might cause slightly slower communication.
+
+ i2c-scl-falling-time-ns:
+ default: 300
+ description:
+ Number of nanoseconds the SCL signal takes to fall
+ (t(f) in the I2C specification). If not specified this is assumed to
+ be the maximum the specification allows (300 ns) which might cause
+ slightly slower communication.
+
+ i2c-sda-falling-time-ns:
+ default: 300
+ description:
+ Number of nanoseconds the SDA signal takes to fall
+ (t(f) in the I2C specification). If not specified we will use the SCL
+ value since they are the same in nearly all cases.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - rockchip,rk3066-i2c
+ - rockchip,rk3188-i2c
+
+then:
+ required:
+ - rockchip,grf
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3188-cru-common.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c0: i2c@2002d000 {
+ compatible = "rockchip,rk3188-i2c";
+ reg = <0x2002d000 0x1000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_I2C0>;
+ clock-names = "i2c";
+ rockchip,grf = <&grf>;
+ i2c-scl-falling-time-ns = <100>;
+ i2c-scl-rising-time-ns = <800>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-uniphier-f.txt b/Documentation/devicetree/bindings/i2c/i2c-uniphier-f.txt
deleted file mode 100644
index 27fc6f8c798b..000000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-uniphier-f.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-UniPhier I2C controller (FIFO-builtin)
-
-Required properties:
-- compatible: should be "socionext,uniphier-fi2c".
-- #address-cells: should be 1.
-- #size-cells: should be 0.
-- reg: offset and length of the register set for the device.
-- interrupts: a single interrupt specifier.
-- clocks: phandle to the input clock.
-
-Optional properties:
-- clock-frequency: desired I2C bus frequency in Hz. The maximum supported
- value is 400000. Defaults to 100000 if not specified.
-
-Examples:
-
- i2c0: i2c@58780000 {
- compatible = "socionext,uniphier-fi2c";
- reg = <0x58780000 0x80>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 4>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-uniphier.txt b/Documentation/devicetree/bindings/i2c/i2c-uniphier.txt
deleted file mode 100644
index 26f9d95b3436..000000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-uniphier.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-UniPhier I2C controller (FIFO-less)
-
-Required properties:
-- compatible: should be "socionext,uniphier-i2c".
-- #address-cells: should be 1.
-- #size-cells: should be 0.
-- reg: offset and length of the register set for the device.
-- interrupts: a single interrupt specifier.
-- clocks: phandle to the input clock.
-
-Optional properties:
-- clock-frequency: desired I2C bus frequency in Hz. The maximum supported
- value is 400000. Defaults to 100000 if not specified.
-
-Examples:
-
- i2c0: i2c@58400000 {
- compatible = "socionext,uniphier-i2c";
- reg = <0x58400000 0x40>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <0 41 1>;
- clocks = <&i2c_clk>;
- clock-frequency = <100000>;
- };
diff --git a/Documentation/devicetree/bindings/i2c/socionext,uniphier-fi2c.yaml b/Documentation/devicetree/bindings/i2c/socionext,uniphier-fi2c.yaml
new file mode 100644
index 000000000000..15abc022968e
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/socionext,uniphier-fi2c.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/socionext,uniphier-fi2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UniPhier I2C controller (FIFO-builtin)
+
+maintainers:
+ - Masahiro Yamada <yamada.masahiro@socionext.com>
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+ compatible:
+ const: socionext,uniphier-fi2c
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-frequency:
+ minimum: 100000
+ maximum: 400000
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - interrupts
+ - clocks
+
+examples:
+ - |
+ i2c0: i2c@58780000 {
+ compatible = "socionext,uniphier-fi2c";
+ reg = <0x58780000 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 4>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
diff --git a/Documentation/devicetree/bindings/i2c/socionext,uniphier-i2c.yaml b/Documentation/devicetree/bindings/i2c/socionext,uniphier-i2c.yaml
new file mode 100644
index 000000000000..ef998def554e
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/socionext,uniphier-i2c.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/socionext,uniphier-i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UniPhier I2C controller (FIFO-less)
+
+maintainers:
+ - Masahiro Yamada <yamada.masahiro@socionext.com>
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+ compatible:
+ const: socionext,uniphier-i2c
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-frequency:
+ minimum: 100000
+ maximum: 400000
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - interrupts
+ - clocks
+
+examples:
+ - |
+ i2c0: i2c@58400000 {
+ compatible = "socionext,uniphier-i2c";
+ reg = <0x58400000 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 41 1>;
+ clocks = <&i2c_clk>;
+ clock-frequency = <100000>;
+ };
diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml
index c602b6fe1c0c..d124eba1ce54 100644
--- a/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml
+++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml
@@ -17,9 +17,13 @@ description: |
properties:
compatible:
- enum:
- - adi,adxl345
- - adi,adxl375
+ oneOf:
+ - items:
+ - const: adi,adxl346
+ - const: adi,adxl345
+ - enum:
+ - adi,adxl345
+ - adi,adxl375
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml b/Documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml
index c1c6d6f223cf..8723a336229e 100644
--- a/Documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml
+++ b/Documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml
@@ -36,6 +36,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/gpio/gpio.h>
diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
index 84d25bd39488..d0913034b1d8 100644
--- a/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7192.yaml
@@ -106,7 +106,6 @@ examples:
spi-cpha;
clocks = <&ad7192_mclk>;
clock-names = "mclk";
- #interrupt-cells = <2>;
interrupts = <25 0x2>;
interrupt-parent = <&gpio>;
dvdd-supply = <&dvdd>;
diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml
index 9acde6d2e2d9..a67ba67dab51 100644
--- a/Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7780.yaml
@@ -67,6 +67,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/gpio/gpio.h>
diff --git a/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml b/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml
index 91ab9c842273..77605f17901c 100644
--- a/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml
@@ -53,6 +53,8 @@ required:
- dout-gpios
- avdd-supply
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/gpio/gpio.h>
diff --git a/Documentation/devicetree/bindings/iio/adc/lltc,ltc2496.yaml b/Documentation/devicetree/bindings/iio/adc/lltc,ltc2496.yaml
index 59009997dca0..118809a03279 100644
--- a/Documentation/devicetree/bindings/iio/adc/lltc,ltc2496.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/lltc,ltc2496.yaml
@@ -32,6 +32,8 @@ required:
- vref-supply
- reg
+additionalProperties: false
+
examples:
- |
spi {
diff --git a/Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml b/Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml
index 0ce290473fb0..8ffeceb6abae 100644
--- a/Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/microchip,mcp3911.yaml
@@ -52,6 +52,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
spi {
diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
index acf36eef728b..b1627441a0b2 100644
--- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
@@ -69,6 +69,8 @@ required:
- "#address-cells"
- "#size-cells"
+additionalProperties: false
+
patternProperties:
"^filter@[0-9]+$":
type: object
diff --git a/Documentation/devicetree/bindings/iio/chemical/plantower,pms7003.yaml b/Documentation/devicetree/bindings/iio/chemical/plantower,pms7003.yaml
index 19e53930ebf6..1fe561574019 100644
--- a/Documentation/devicetree/bindings/iio/chemical/plantower,pms7003.yaml
+++ b/Documentation/devicetree/bindings/iio/chemical/plantower,pms7003.yaml
@@ -38,6 +38,8 @@ required:
- compatible
- vcc-supply
+additionalProperties: false
+
examples:
- |
serial {
diff --git a/Documentation/devicetree/bindings/iio/chemical/sensirion,sps30.yaml b/Documentation/devicetree/bindings/iio/chemical/sensirion,sps30.yaml
index 50a50a0d7070..a93d1972a5c2 100644
--- a/Documentation/devicetree/bindings/iio/chemical/sensirion,sps30.yaml
+++ b/Documentation/devicetree/bindings/iio/chemical/sensirion,sps30.yaml
@@ -24,6 +24,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
i2c {
diff --git a/Documentation/devicetree/bindings/iio/dac/lltc,ltc1660.yaml b/Documentation/devicetree/bindings/iio/dac/lltc,ltc1660.yaml
index a285eaba7125..e51a585bd5a3 100644
--- a/Documentation/devicetree/bindings/iio/dac/lltc,ltc1660.yaml
+++ b/Documentation/devicetree/bindings/iio/dac/lltc,ltc1660.yaml
@@ -34,6 +34,8 @@ required:
- reg
- vref-supply
+additionalProperties: false
+
examples:
- |
spi {
diff --git a/Documentation/devicetree/bindings/iio/light/adux1020.yaml b/Documentation/devicetree/bindings/iio/light/adux1020.yaml
index 69bd5c06319d..d7d14f2f1c20 100644
--- a/Documentation/devicetree/bindings/iio/light/adux1020.yaml
+++ b/Documentation/devicetree/bindings/iio/light/adux1020.yaml
@@ -28,6 +28,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
diff --git a/Documentation/devicetree/bindings/iio/light/bh1750.yaml b/Documentation/devicetree/bindings/iio/light/bh1750.yaml
index 1cc60d7ecfa0..1a88b3c253d5 100644
--- a/Documentation/devicetree/bindings/iio/light/bh1750.yaml
+++ b/Documentation/devicetree/bindings/iio/light/bh1750.yaml
@@ -28,6 +28,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
i2c {
diff --git a/Documentation/devicetree/bindings/iio/light/isl29018.yaml b/Documentation/devicetree/bindings/iio/light/isl29018.yaml
index cbb00be8f359..0ea278b07d1c 100644
--- a/Documentation/devicetree/bindings/iio/light/isl29018.yaml
+++ b/Documentation/devicetree/bindings/iio/light/isl29018.yaml
@@ -38,6 +38,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
diff --git a/Documentation/devicetree/bindings/iio/light/noa1305.yaml b/Documentation/devicetree/bindings/iio/light/noa1305.yaml
index 17e7f140b69b..fe7bfe1adbda 100644
--- a/Documentation/devicetree/bindings/iio/light/noa1305.yaml
+++ b/Documentation/devicetree/bindings/iio/light/noa1305.yaml
@@ -29,6 +29,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
i2c {
diff --git a/Documentation/devicetree/bindings/iio/light/stk33xx.yaml b/Documentation/devicetree/bindings/iio/light/stk33xx.yaml
index aae8a6d627c9..f92bf7b2b7f0 100644
--- a/Documentation/devicetree/bindings/iio/light/stk33xx.yaml
+++ b/Documentation/devicetree/bindings/iio/light/stk33xx.yaml
@@ -30,6 +30,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
diff --git a/Documentation/devicetree/bindings/iio/light/tsl2583.yaml b/Documentation/devicetree/bindings/iio/light/tsl2583.yaml
index e86ef64ecf03..7b92ba8cbb9f 100644
--- a/Documentation/devicetree/bindings/iio/light/tsl2583.yaml
+++ b/Documentation/devicetree/bindings/iio/light/tsl2583.yaml
@@ -32,6 +32,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
i2c {
diff --git a/Documentation/devicetree/bindings/iio/light/tsl2772.yaml b/Documentation/devicetree/bindings/iio/light/tsl2772.yaml
index ed2c3d5eadf5..e8f7d1ada57b 100644
--- a/Documentation/devicetree/bindings/iio/light/tsl2772.yaml
+++ b/Documentation/devicetree/bindings/iio/light/tsl2772.yaml
@@ -62,6 +62,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
diff --git a/Documentation/devicetree/bindings/iio/light/veml6030.yaml b/Documentation/devicetree/bindings/iio/light/veml6030.yaml
index 0ff9b11f9d18..fb19a2d7a849 100644
--- a/Documentation/devicetree/bindings/iio/light/veml6030.yaml
+++ b/Documentation/devicetree/bindings/iio/light/veml6030.yaml
@@ -45,6 +45,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
diff --git a/Documentation/devicetree/bindings/iio/pressure/asc,dlhl60d.yaml b/Documentation/devicetree/bindings/iio/pressure/asc,dlhl60d.yaml
index 9f5ca9c42025..64c18f1693f0 100644
--- a/Documentation/devicetree/bindings/iio/pressure/asc,dlhl60d.yaml
+++ b/Documentation/devicetree/bindings/iio/pressure/asc,dlhl60d.yaml
@@ -33,6 +33,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
diff --git a/Documentation/devicetree/bindings/iio/pressure/bmp085.yaml b/Documentation/devicetree/bindings/iio/pressure/bmp085.yaml
index 519137e5c170..49257f9251e8 100644
--- a/Documentation/devicetree/bindings/iio/pressure/bmp085.yaml
+++ b/Documentation/devicetree/bindings/iio/pressure/bmp085.yaml
@@ -25,6 +25,9 @@ properties:
- bosch,bmp280
- bosch,bme280
+ reg:
+ maxItems: 1
+
vddd-supply:
description:
digital voltage regulator (see regulator/regulator.txt)
@@ -49,6 +52,8 @@ required:
- vddd-supply
- vdda-supply
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/gpio/gpio.h>
diff --git a/Documentation/devicetree/bindings/iio/proximity/devantech-srf04.yaml b/Documentation/devicetree/bindings/iio/proximity/devantech-srf04.yaml
index 8afbac24c34e..f86f8b23ef18 100644
--- a/Documentation/devicetree/bindings/iio/proximity/devantech-srf04.yaml
+++ b/Documentation/devicetree/bindings/iio/proximity/devantech-srf04.yaml
@@ -74,6 +74,8 @@ required:
- trig-gpios
- echo-gpios
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/gpio/gpio.h>
diff --git a/Documentation/devicetree/bindings/iio/proximity/parallax-ping.yaml b/Documentation/devicetree/bindings/iio/proximity/parallax-ping.yaml
index a079c9921af6..ada55f186f3c 100644
--- a/Documentation/devicetree/bindings/iio/proximity/parallax-ping.yaml
+++ b/Documentation/devicetree/bindings/iio/proximity/parallax-ping.yaml
@@ -42,6 +42,8 @@ required:
- compatible
- ping-gpios
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/gpio/gpio.h>
diff --git a/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml b/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml
index d4922f9f0376..8fb46de6641d 100644
--- a/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml
+++ b/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml
@@ -123,12 +123,11 @@ patternProperties:
sign.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint64-matrix
+ minItems: 3
+ maxItems: 64
items:
- minItems: 3
- maxItems: 64
- items:
- minItems: 2
- maxItems: 2
+ minItems: 2
+ maxItems: 2
"^diode@":
type: object
@@ -328,12 +327,11 @@ patternProperties:
78 and 79.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint64-matrix
+ minItems: 3
+ maxItems: 64
items:
- minItems: 3
- maxItems: 64
- items:
- minItems: 2
- maxItems: 2
+ minItems: 2
+ maxItems: 2
adi,custom-steinhart:
description:
@@ -398,6 +396,8 @@ required:
- reg
- interrupts
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
@@ -463,16 +463,16 @@ examples:
adi,sensor-type = <9>; //custom thermocouple
adi,single-ended;
adi,custom-thermocouple = /bits/ 64
- <(-50220000) 0
- (-30200000) 99100000
- (-5300000) 135400000
- 0 273150000
- 40200000 361200000
- 55300000 522100000
- 88300000 720300000
- 132200000 811200000
- 188700000 922500000
- 460400000 1000000000>; //10 pairs
+ <(-50220000) 0>,
+ <(-30200000) 99100000>,
+ <(-5300000) 135400000>,
+ <0 273150000>,
+ <40200000 361200000>,
+ <55300000 522100000>,
+ <88300000 720300000>,
+ <132200000 811200000>,
+ <188700000 922500000>,
+ <460400000 1000000000>; //10 pairs
};
};
diff --git a/Documentation/devicetree/bindings/input/gpio-vibrator.yaml b/Documentation/devicetree/bindings/input/gpio-vibrator.yaml
index b98bf9363c8f..2384465eaa19 100644
--- a/Documentation/devicetree/bindings/input/gpio-vibrator.yaml
+++ b/Documentation/devicetree/bindings/input/gpio-vibrator.yaml
@@ -26,6 +26,8 @@ required:
- compatible
- enable-gpios
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/gpio/gpio.h>
diff --git a/Documentation/devicetree/bindings/input/max77650-onkey.yaml b/Documentation/devicetree/bindings/input/max77650-onkey.yaml
index 2f2e0b6ebbbd..3a2ad6ec64db 100644
--- a/Documentation/devicetree/bindings/input/max77650-onkey.yaml
+++ b/Documentation/devicetree/bindings/input/max77650-onkey.yaml
@@ -33,3 +33,6 @@ properties:
required:
- compatible
+additionalProperties: false
+
+...
diff --git a/Documentation/devicetree/bindings/input/st,stpmic1-onkey.txt b/Documentation/devicetree/bindings/input/st,stpmic1-onkey.txt
deleted file mode 100644
index eb8e83736c02..000000000000
--- a/Documentation/devicetree/bindings/input/st,stpmic1-onkey.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-STMicroelectronics STPMIC1 Onkey
-
-Required properties:
-
-- compatible = "st,stpmic1-onkey";
-- interrupts: interrupt line to use
-- interrupt-names = "onkey-falling", "onkey-rising"
- onkey-falling: happens when onkey is pressed; IT_PONKEY_F of pmic
- onkey-rising: happens when onkey is released; IT_PONKEY_R of pmic
-
-Optional properties:
-
-- st,onkey-clear-cc-flag: onkey is able power on after an
- over-current shutdown event.
-- st,onkey-pu-inactive: onkey pull up is not active
-- power-off-time-sec: Duration in seconds which the key should be kept
- pressed for device to power off automatically (from 1 to 16 seconds).
- see See Documentation/devicetree/bindings/input/input.yaml
-
-Example:
-
-onkey {
- compatible = "st,stpmic1-onkey";
- interrupt-parent = <&pmic>;
- interrupts = <IT_PONKEY_F 0>,<IT_PONKEY_R 1>;
- interrupt-names = "onkey-falling", "onkey-rising";
- power-off-time-sec = <10>;
-};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml
index 507c141ea760..ccc507f384d2 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml
@@ -44,6 +44,8 @@ required:
- interrupt-controller
- '#interrupt-cells'
+additionalProperties: false
+
examples:
- |
intcon: interrupt-controller@c8003000 {
diff --git a/Documentation/devicetree/bindings/interrupt-controller/msi.txt b/Documentation/devicetree/bindings/interrupt-controller/msi.txt
index c60c034dcf19..c20b51df7138 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/msi.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/msi.txt
@@ -98,7 +98,7 @@ Example
};
msi_c: msi-controller@c {
- reg = <0xb 0xf00>;
+ reg = <0xc 0xf00>;
compatible = "vendor-b,another-controller";
msi-controller;
/* Each device has some unique ID */
diff --git a/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.txt b/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.txt
deleted file mode 100644
index 48e71d3ac2ad..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-UniPhier AIDET
-
-UniPhier AIDET (ARM Interrupt Detector) is an add-on block for ARM GIC (Generic
-Interrupt Controller). GIC itself can handle only high level and rising edge
-interrupts. The AIDET provides logic inverter to support low level and falling
-edge interrupts.
-
-Required properties:
-- compatible: Should be one of the following:
- "socionext,uniphier-ld4-aidet" - for LD4 SoC
- "socionext,uniphier-pro4-aidet" - for Pro4 SoC
- "socionext,uniphier-sld8-aidet" - for sLD8 SoC
- "socionext,uniphier-pro5-aidet" - for Pro5 SoC
- "socionext,uniphier-pxs2-aidet" - for PXs2/LD6b SoC
- "socionext,uniphier-ld11-aidet" - for LD11 SoC
- "socionext,uniphier-ld20-aidet" - for LD20 SoC
- "socionext,uniphier-pxs3-aidet" - for PXs3 SoC
-- reg: Specifies offset and length of the register set for the device.
-- interrupt-controller: Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an interrupt
- source. The value should be 2. The first cell defines the interrupt number
- (corresponds to the SPI interrupt number of GIC). The second cell specifies
- the trigger type as defined in interrupts.txt in this directory.
-
-Example:
-
- aidet: aidet@5fc20000 {
- compatible = "socionext,uniphier-pro4-aidet";
- reg = <0x5fc20000 0x200>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.yaml b/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.yaml
new file mode 100644
index 000000000000..f89ebde76dab
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/socionext,uniphier-aidet.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UniPhier AIDET
+
+description: |
+ UniPhier AIDET (ARM Interrupt Detector) is an add-on block for ARM GIC
+ (Generic Interrupt Controller). GIC itself can handle only high level and
+ rising edge interrupts. The AIDET provides logic inverter to support low
+ level and falling edge interrupts.
+
+maintainers:
+ - Masahiro Yamada <yamada.masahiro@socionext.com>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - socionext,uniphier-ld4-aidet
+ - socionext,uniphier-pro4-aidet
+ - socionext,uniphier-sld8-aidet
+ - socionext,uniphier-pro5-aidet
+ - socionext,uniphier-pxs2-aidet
+ - socionext,uniphier-ld6b-aidet
+ - socionext,uniphier-ld11-aidet
+ - socionext,uniphier-ld20-aidet
+ - socionext,uniphier-pxs3-aidet
+
+ reg:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ description: |
+ The first cell defines the interrupt number (corresponds to the SPI
+ interrupt number of GIC). The second cell specifies the trigger type as
+ defined in interrupts.txt in this directory.
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - '#interrupt-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ interrupt-controller@5fc20000 {
+ compatible = "socionext,uniphier-pro4-aidet";
+ reg = <0x5fc20000 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
diff --git a/Documentation/devicetree/bindings/iommu/samsung,sysmmu.yaml b/Documentation/devicetree/bindings/iommu/samsung,sysmmu.yaml
index 7cdd3aaa2ba4..0e33cd9e010e 100644
--- a/Documentation/devicetree/bindings/iommu/samsung,sysmmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/samsung,sysmmu.yaml
@@ -80,6 +80,8 @@ required:
- clock-names
- "#iommu-cells"
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/exynos5250.h>
diff --git a/Documentation/devicetree/bindings/leds/common.yaml b/Documentation/devicetree/bindings/leds/common.yaml
index c60b994fe116..4c270fde4567 100644
--- a/Documentation/devicetree/bindings/leds/common.yaml
+++ b/Documentation/devicetree/bindings/leds/common.yaml
@@ -167,13 +167,13 @@ examples:
led-controller {
compatible = "gpio-leds";
- led0 {
+ led-0 {
function = LED_FUNCTION_STATUS;
linux,default-trigger = "heartbeat";
gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
};
- led1 {
+ led-1 {
function = LED_FUNCTION_USB;
gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
trigger-sources = <&ohci_port1>, <&ehci_port1>;
diff --git a/Documentation/devicetree/bindings/leds/leds-max77650.yaml b/Documentation/devicetree/bindings/leds/leds-max77650.yaml
index 8c43f1e1bf7d..c6f96cabd4d1 100644
--- a/Documentation/devicetree/bindings/leds/leds-max77650.yaml
+++ b/Documentation/devicetree/bindings/leds/leds-max77650.yaml
@@ -49,3 +49,6 @@ required:
- compatible
- "#address-cells"
- "#size-cells"
+additionalProperties: false
+
+...
diff --git a/Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml b/Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml
index b50f4bcc98f1..90edf9d33b33 100644
--- a/Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml
+++ b/Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml
@@ -50,3 +50,6 @@ patternProperties:
required:
- compatible
+additionalProperties: false
+
+...
diff --git a/Documentation/devicetree/bindings/mailbox/amlogic,meson-gxbb-mhu.yaml b/Documentation/devicetree/bindings/mailbox/amlogic,meson-gxbb-mhu.yaml
index 319280563648..aa2b3bf56b57 100644
--- a/Documentation/devicetree/bindings/mailbox/amlogic,meson-gxbb-mhu.yaml
+++ b/Documentation/devicetree/bindings/mailbox/amlogic,meson-gxbb-mhu.yaml
@@ -41,6 +41,8 @@ required:
- interrupts
- "#mbox-cells"
+additionalProperties: false
+
examples:
- |
mailbox@c883c404 {
diff --git a/Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml b/Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml
index 335717e15970..37d77e065491 100644
--- a/Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml
+++ b/Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml
@@ -124,6 +124,8 @@ required:
- amlogic,ao-sysctrl
- amlogic,canvas
+additionalProperties: false
+
examples:
- |
vdec: video-decoder@c8820000 {
diff --git a/Documentation/devicetree/bindings/media/amlogic,meson-gx-ao-cec.yaml b/Documentation/devicetree/bindings/media/amlogic,meson-gx-ao-cec.yaml
index 41197578f19a..95ffa8bc0533 100644
--- a/Documentation/devicetree/bindings/media/amlogic,meson-gx-ao-cec.yaml
+++ b/Documentation/devicetree/bindings/media/amlogic,meson-gx-ao-cec.yaml
@@ -24,6 +24,12 @@ properties:
reg:
maxItems: 1
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ maxItems: 1
+
interrupts:
maxItems: 1
@@ -47,7 +53,6 @@ allOf:
- description: AO-CEC clock
clock-names:
- maxItems: 1
items:
- const: core
@@ -66,7 +71,6 @@ allOf:
- description: AO-CEC clock generator source
clock-names:
- maxItems: 1
items:
- const: oscin
@@ -78,6 +82,8 @@ required:
- clocks
- clock-names
+additionalProperties: false
+
examples:
- |
cec_AO: cec@100 {
@@ -88,4 +94,3 @@ examples:
clock-names = "core";
hdmi-phandle = <&hdmi_tx>;
};
-
diff --git a/Documentation/devicetree/bindings/media/renesas,ceu.yaml b/Documentation/devicetree/bindings/media/renesas,ceu.yaml
index 8e9251a0f9ef..fcb5f13704a5 100644
--- a/Documentation/devicetree/bindings/media/renesas,ceu.yaml
+++ b/Documentation/devicetree/bindings/media/renesas,ceu.yaml
@@ -59,6 +59,8 @@ required:
- interrupts
- port
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/Documentation/devicetree/bindings/media/renesas,vin.txt b/Documentation/devicetree/bindings/media/renesas,vin.txt
deleted file mode 100644
index 5eefd62ac5c5..000000000000
--- a/Documentation/devicetree/bindings/media/renesas,vin.txt
+++ /dev/null
@@ -1,217 +0,0 @@
-Renesas R-Car Video Input driver (rcar_vin)
--------------------------------------------
-
-The rcar_vin device provides video input capabilities for the Renesas R-Car
-family of devices.
-
-Each VIN instance has a single parallel input that supports RGB and YUV video,
-with both external synchronization and BT.656 synchronization for the latter.
-Depending on the instance the VIN input is connected to external SoC pins, or
-on Gen3 and RZ/G2 platforms to a CSI-2 receiver.
-
- - compatible: Must be one or more of the following
- - "renesas,vin-r8a7743" for the R8A7743 device
- - "renesas,vin-r8a7744" for the R8A7744 device
- - "renesas,vin-r8a7745" for the R8A7745 device
- - "renesas,vin-r8a77470" for the R8A77470 device
- - "renesas,vin-r8a774a1" for the R8A774A1 device
- - "renesas,vin-r8a774b1" for the R8A774B1 device
- - "renesas,vin-r8a774c0" for the R8A774C0 device
- - "renesas,vin-r8a7778" for the R8A7778 device
- - "renesas,vin-r8a7779" for the R8A7779 device
- - "renesas,vin-r8a7790" for the R8A7790 device
- - "renesas,vin-r8a7791" for the R8A7791 device
- - "renesas,vin-r8a7792" for the R8A7792 device
- - "renesas,vin-r8a7793" for the R8A7793 device
- - "renesas,vin-r8a7794" for the R8A7794 device
- - "renesas,vin-r8a7795" for the R8A7795 device
- - "renesas,vin-r8a7796" for the R8A7796 device
- - "renesas,vin-r8a77965" for the R8A77965 device
- - "renesas,vin-r8a77970" for the R8A77970 device
- - "renesas,vin-r8a77980" for the R8A77980 device
- - "renesas,vin-r8a77990" for the R8A77990 device
- - "renesas,vin-r8a77995" for the R8A77995 device
- - "renesas,rcar-gen2-vin" for a generic R-Car Gen2 or RZ/G1 compatible
- device.
-
- When compatible with the generic version nodes must list the
- SoC-specific version corresponding to the platform first
- followed by the generic version.
-
- - reg: the register base and size for the device registers
- - interrupts: the interrupt for the device
- - clocks: Reference to the parent clock
-
-The per-board settings for Gen2 and RZ/G1 platforms:
-
-- port - sub-node describing a single endpoint connected to the VIN
- from external SoC pins as described in video-interfaces.txt[1].
- Only the first one will be considered as each vin interface has one
- input port.
-
- - Optional properties for endpoint nodes:
- - hsync-active: see [1] for description. Default is active high.
- - vsync-active: see [1] for description. Default is active high.
- If both HSYNC and VSYNC polarities are not specified, embedded
- synchronization is selected.
- - field-active-even: see [1] for description. Default is active high.
- - bus-width: see [1] for description. The selected bus width depends on
- the SoC type and selected input image format.
- Valid values are: 8, 10, 12, 16, 24 and 32.
- - data-shift: see [1] for description. Valid values are 0 and 8.
- - data-enable-active: polarity of CLKENB signal, see [1] for
- description. Default is active high.
-
-The per-board settings for Gen3 and RZ/G2 platforms:
-
-Gen3 and RZ/G2 platforms can support both a single connected parallel input
-source from external SoC pins (port@0) and/or multiple parallel input sources
-from local SoC CSI-2 receivers (port@1) depending on SoC.
-
-- renesas,id - ID number of the VIN, VINx in the documentation.
-- ports
- - port@0 - sub-node describing a single endpoint connected to the VIN
- from external SoC pins as described in video-interfaces.txt[1].
- Describing more than one endpoint in port@0 is invalid. Only VIN
- instances that are connected to external pins should have port@0.
-
- Endpoint nodes of port@0 support the optional properties listed in
- the Gen2 per-board settings description.
-
- - port@1 - sub-nodes describing one or more endpoints connected to
- the VIN from local SoC CSI-2 receivers. The endpoint numbers must
- use the following schema.
-
- - endpoint@0 - sub-node describing the endpoint connected to CSI20
- - endpoint@1 - sub-node describing the endpoint connected to CSI21
- - endpoint@2 - sub-node describing the endpoint connected to CSI40
- - endpoint@3 - sub-node describing the endpoint connected to CSI41
-
- Endpoint nodes of port@1 do not support any optional endpoint property.
-
-Device node example for Gen2 platforms
---------------------------------------
-
- aliases {
- vin0 = &vin0;
- };
-
- vin0: vin@e6ef0000 {
- compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin";
- clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
- reg = <0 0xe6ef0000 0 0x1000>;
- interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
-Board setup example for Gen2 platforms (vin1 composite video input)
--------------------------------------------------------------------
-
-&i2c2 {
- status = "okay";
- pinctrl-0 = <&i2c2_pins>;
- pinctrl-names = "default";
-
- adv7180@20 {
- compatible = "adi,adv7180";
- reg = <0x20>;
- remote = <&vin1>;
-
- port {
- adv7180: endpoint {
- bus-width = <8>;
- remote-endpoint = <&vin1ep0>;
- };
- };
- };
-};
-
-/* composite video input */
-&vin1 {
- pinctrl-0 = <&vin1_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- port {
- vin1ep0: endpoint {
- remote-endpoint = <&adv7180>;
- bus-width = <8>;
- };
- };
-};
-
-Device node example for Gen3 platforms
---------------------------------------
-
- vin0: video@e6ef0000 {
- compatible = "renesas,vin-r8a7795";
- reg = <0 0xe6ef0000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 811>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 811>;
- renesas,id = <0>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- vin0csi20: endpoint@0 {
- reg = <0>;
- remote-endpoint= <&csi20vin0>;
- };
- vin0csi21: endpoint@1 {
- reg = <1>;
- remote-endpoint= <&csi21vin0>;
- };
- vin0csi40: endpoint@2 {
- reg = <2>;
- remote-endpoint= <&csi40vin0>;
- };
- };
- };
- };
-
- csi20: csi2@fea80000 {
- compatible = "renesas,r8a7795-csi2";
- reg = <0 0xfea80000 0 0x10000>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 714>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
- resets = <&cpg 714>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- csi20_in: endpoint {
- clock-lanes = <0>;
- data-lanes = <1>;
- remote-endpoint = <&adv7482_txb>;
- };
- };
-
- port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- reg = <1>;
-
- csi20vin0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&vin0csi20>;
- };
- };
- };
- };
-
-[1] video-interfaces.txt common video media interface
diff --git a/Documentation/devicetree/bindings/media/renesas,vin.yaml b/Documentation/devicetree/bindings/media/renesas,vin.yaml
new file mode 100644
index 000000000000..1ec947b4781f
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/renesas,vin.yaml
@@ -0,0 +1,402 @@
+# SPDX-License-Identifier: GPL-2.0-only
+# Copyright (C) 2020 Renesas Electronics Corp.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/renesas,vin.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car Video Input (VIN)
+
+maintainers:
+ - Niklas Söderlund <niklas.soderlund@ragnatech.se>
+
+description:
+ The R-Car Video Input (VIN) device provides video input capabilities for the
+ Renesas R-Car family of devices.
+
+ Each VIN instance has a single parallel input that supports RGB and YUV video,
+ with both external synchronization and BT.656 synchronization for the latter.
+ Depending on the instance the VIN input is connected to external SoC pins, or
+ on Gen3 and RZ/G2 platforms to a CSI-2 receiver.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - renesas,vin-r8a7743 # RZ/G1M
+ - renesas,vin-r8a7744 # RZ/G1N
+ - renesas,vin-r8a7745 # RZ/G1E
+ - renesas,vin-r8a77470 # RZ/G1C
+ - renesas,vin-r8a7790 # R-Car H2
+ - renesas,vin-r8a7791 # R-Car M2-W
+ - renesas,vin-r8a7792 # R-Car V2H
+ - renesas,vin-r8a7793 # R-Car M2-N
+ - renesas,vin-r8a7794 # R-Car E2
+ - const: renesas,rcar-gen2-vin # Generic R-Car Gen2 or RZ/G1
+
+ - items:
+ - enum:
+ - renesas,vin-r8a774a1 # RZ/G2M
+ - renesas,vin-r8a774b1 # RZ/G2N
+ - renesas,vin-r8a774c0 # RZ/G2E
+ - renesas,vin-r8a7778 # R-Car M1
+ - renesas,vin-r8a7779 # R-Car H1
+ - renesas,vin-r8a7795 # R-Car H3
+ - renesas,vin-r8a7796 # R-Car M3-W
+ - renesas,vin-r8a77965 # R-Car M3-N
+ - renesas,vin-r8a77970 # R-Car V3M
+ - renesas,vin-r8a77980 # R-Car V3H
+ - renesas,vin-r8a77990 # R-Car E3
+ - renesas,vin-r8a77995 # R-Car D3
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ #The per-board settings for Gen2 and RZ/G1 platforms:
+ port:
+ type: object
+ description:
+ A node containing a parallel input with a single endpoint definitions as
+ documented in
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+
+ properties:
+ endpoint:
+ type: object
+
+ properties:
+ hsync-active:
+ description:
+ If both HSYNC and VSYNC polarities are not specified, embedded
+ synchronization is selected.
+ default: 1
+
+ vsync-active:
+ description:
+ If both HSYNC and VSYNC polarities are not specified, embedded
+ synchronization is selected.
+ default: 1
+
+ field-active-even: true
+
+ bus-width: true
+
+ data-shift: true
+
+ data-enable-active:
+ description: Polarity of CLKENB signal
+ default: 1
+
+ pclk-sample: true
+
+ data-active: true
+
+ remote-endpoint: true
+
+ required:
+ - remote-endpoint
+
+ additionalProperties: false
+
+ additionalProperties: false
+
+ #The per-board settings for Gen3 and RZ/G2 platforms:
+ renesas,id:
+ description: VIN channel number
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - minimum: 0
+ - maximum: 15
+
+ ports:
+ type: object
+ description:
+ A node containing input nodes with endpoint definitions as documented in
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+
+ properties:
+ port@0:
+ type: object
+ description:
+ Input port node, single endpoint describing a parallel input source.
+
+ properties:
+ reg:
+ const: 0
+
+ endpoint:
+ type: object
+
+ properties:
+ hsync-active:
+ description:
+ If both HSYNC and VSYNC polarities are not specified, embedded
+ synchronization is selected.
+ default: 1
+
+ vsync-active:
+ description:
+ If both HSYNC and VSYNC polarities are not specified, embedded
+ synchronization is selected.
+ default: 1
+
+ field-active-even: true
+
+ bus-width: true
+
+ data-shift: true
+
+ data-enable-active:
+ description: Polarity of CLKENB signal
+ default: 1
+
+ pclk-sample: true
+
+ data-active: true
+
+ remote-endpoint: true
+
+ required:
+ - remote-endpoint
+
+ additionalProperties: false
+
+ required:
+ - endpoint
+
+ additionalProperties: false
+
+ port@1:
+ type: object
+ description:
+ Input port node, multiple endpoints describing all the R-Car CSI-2
+ modules connected the VIN.
+
+ properties:
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ reg:
+ const: 1
+
+ endpoint@0:
+ type: object
+ description: Endpoint connected to CSI20.
+
+ properties:
+ reg:
+ const: 0
+
+ remote-endpoint: true
+
+ required:
+ - reg
+ - remote-endpoint
+
+ additionalProperties: false
+
+ endpoint@1:
+ type: object
+ description: Endpoint connected to CSI21.
+
+ properties:
+ reg:
+ const: 1
+
+ remote-endpoint: true
+
+ required:
+ - reg
+ - remote-endpoint
+
+ additionalProperties: false
+
+ endpoint@2:
+ type: object
+ description: Endpoint connected to CSI40.
+
+ properties:
+ reg:
+ const: 2
+
+ remote-endpoint: true
+
+ required:
+ - reg
+ - remote-endpoint
+
+ additionalProperties: false
+
+ endpoint@3:
+ type: object
+ description: Endpoint connected to CSI41.
+
+ properties:
+ reg:
+ const: 3
+
+ remote-endpoint: true
+
+ required:
+ - reg
+ - remote-endpoint
+
+ additionalProperties: false
+
+ anyOf:
+ - required:
+ - endpoint@0
+ - required:
+ - endpoint@1
+ - required:
+ - endpoint@2
+ - required:
+ - endpoint@3
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - power-domains
+ - resets
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,vin-r8a7778
+ - renesas,vin-r8a7779
+ - renesas,rcar-gen2-vin
+then:
+ required:
+ - port
+else:
+ required:
+ - renesas,id
+ - ports
+
+additionalProperties: false
+
+examples:
+ # Device node example for Gen2 platform
+ - |
+ #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7790-sysc.h>
+
+ vin1: vin@e6ef1000 {
+ compatible = "renesas,vin-r8a7790",
+ "renesas,rcar-gen2-vin";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 810>;
+
+ port {
+ vin1ep0: endpoint {
+ remote-endpoint = <&adv7180>;
+ bus-width = <8>;
+ };
+ };
+ };
+
+ # Device node example for Gen3 platform with only CSI-2
+ - |
+ #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7795-sysc.h>
+
+ vin0: video@e6ef0000 {
+ compatible = "renesas,vin-r8a7795";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ renesas,id = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin0csi20: endpoint@0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin0>;
+ };
+ vin0csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin0>;
+ };
+ };
+ };
+ };
+
+ # Device node example for Gen3 platform with CSI-2 and parallel
+ - |
+ #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a77970-sysc.h>
+
+ vin2: video@e6ef2000 {
+ compatible = "renesas,vin-r8a77970";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ renesas,id = <2>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ vin2_in: endpoint {
+ remote-endpoint = <&adv7612_out>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin2csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&csi40vin2>;
+ };
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/mfd/max77650.yaml b/Documentation/devicetree/bindings/mfd/max77650.yaml
index 480385789394..b0a0f0d3d9d4 100644
--- a/Documentation/devicetree/bindings/mfd/max77650.yaml
+++ b/Documentation/devicetree/bindings/mfd/max77650.yaml
@@ -73,6 +73,8 @@ required:
- gpio-controller
- "#gpio-cells"
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml b/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml
index 4fbb9e734284..3a6a1a26e2b3 100644
--- a/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml
+++ b/Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml
@@ -41,6 +41,9 @@ properties:
"#clock-cells":
const: 0
+ clock-output-names:
+ const: bd71828-32k-out
+
rohm,charger-sense-resistor-ohms:
minimum: 10000000
maximum: 50000000
@@ -74,6 +77,8 @@ required:
- gpio-controller
- "#gpio-cells"
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
diff --git a/Documentation/devicetree/bindings/mfd/st,stpmic1.txt b/Documentation/devicetree/bindings/mfd/st,stpmic1.txt
deleted file mode 100644
index afd45c089585..000000000000
--- a/Documentation/devicetree/bindings/mfd/st,stpmic1.txt
+++ /dev/null
@@ -1,61 +0,0 @@
-* STMicroelectronics STPMIC1 Power Management IC
-
-Required properties:
-- compatible: : "st,stpmic1"
-- reg: : The I2C slave address for the STPMIC1 chip.
-- interrupts: : The interrupt line the device is connected to.
-- #interrupt-cells: : Should be 1.
-- interrupt-controller: : Marks the device node as an interrupt controller.
- Interrupt numbers are defined at
- dt-bindings/mfd/st,stpmic1.h.
-
-STPMIC1 consists in a varied group of sub-devices.
-Each sub-device binding is be described in own documentation file.
-
-Device Description
------- ------------
-st,stpmic1-onkey : Power on key, see ../input/st,stpmic1-onkey.txt
-st,stpmic1-regulators : Regulators, see ../regulator/st,stpmic1-regulator.txt
-st,stpmic1-wdt : Watchdog, see ../watchdog/st,stpmic1-wdt.txt
-
-Example:
-
-#include <dt-bindings/mfd/st,stpmic1.h>
-
-pmic: pmic@33 {
- compatible = "st,stpmic1";
- reg = <0x33>;
- interrupt-parent = <&gpioa>;
- interrupts = <0 2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
-
- onkey {
- compatible = "st,stpmic1-onkey";
- interrupts = <IT_PONKEY_F 0>,<IT_PONKEY_R 1>;
- interrupt-names = "onkey-falling", "onkey-rising";
- power-off-time-sec = <10>;
- };
-
- watchdog {
- compatible = "st,stpmic1-wdt";
- };
-
- regulators {
- compatible = "st,stpmic1-regulators";
-
- vdd_core: buck1 {
- regulator-name = "vdd_core";
- regulator-boot-on;
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1200000>;
- };
- vdd: buck3 {
- regulator-name = "vdd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-pull-down;
- };
- };
diff --git a/Documentation/devicetree/bindings/mfd/st,stpmic1.yaml b/Documentation/devicetree/bindings/mfd/st,stpmic1.yaml
new file mode 100644
index 000000000000..d9ad9260e348
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/st,stpmic1.yaml
@@ -0,0 +1,339 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/st,stpmic1.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STMicroelectonics STPMIC1 Power Management IC bindings
+
+description: STMicroelectronics STPMIC1 Power Management IC
+
+maintainers:
+ - pascal Paillet <p.paillet@st.com>
+
+properties:
+ compatible:
+ const: st,stpmic1
+
+ reg:
+ const: 0x33
+
+ interrupts:
+ maxItems: 1
+
+ "#interrupt-cells":
+ const: 2
+
+ interrupt-controller: true
+
+ onkey:
+ type: object
+
+ allOf:
+ - $ref: ../input/input.yaml
+
+ properties:
+ compatible:
+ const: st,stpmic1-onkey
+
+ interrupts:
+ items:
+ - description: onkey-falling, happens when onkey is pressed. IT_PONKEY_F of pmic
+ - description: onkey-rising, happens when onkey is released. IT_PONKEY_R of pmic
+
+ interrupt-names:
+ items:
+ - const: onkey-falling
+ - const: onkey-rising
+
+ st,onkey-clear-cc-flag:
+ description: onkey is able power on after an over-current shutdown event.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ st,onkey-pu-inactive:
+ description: onkey pull up is not active
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ power-off-time-sec:
+ minimum: 1
+ maximum: 16
+
+ required:
+ - compatible
+ - interrupts
+ - interrupt-names
+
+ additionalProperties: false
+
+ watchdog:
+ type: object
+
+ allOf:
+ - $ref: ../watchdog/watchdog.yaml
+
+ properties:
+ compatible:
+ const: st,stpmic1-wdt
+
+ timeout-sec: true
+
+ required:
+ - compatible
+
+ additionalProperties: false
+
+ regulators:
+ type: object
+
+ description: |
+ Available Regulators in STPMIC1 device are:
+ - buck1 for Buck BUCK1
+ - buck2 for Buck BUCK2
+ - buck3 for Buck BUCK3
+ - buck4 for Buck BUCK4
+ - ldo1 for LDO LDO1
+ - ldo2 for LDO LDO2
+ - ldo3 for LDO LDO3
+ - ldo4 for LDO LDO4
+ - ldo5 for LDO LDO5
+ - ldo6 for LDO LDO6
+ - vref_ddr for LDO Vref DDR
+ - boost for Buck BOOST
+ - pwr_sw1 for VBUS_OTG switch
+ - pwr_sw2 for SW_OUT switch
+ Switches are fixed voltage regulators with only enable/disable capability.
+
+ properties:
+ compatible:
+ const: st,stpmic1-regulators
+
+ ldo3:
+ type: object
+
+ properties:
+ interrupts:
+ maxItems: 1
+
+ st,mask-reset:
+ description: mask reset for this regulator,
+ the regulator configuration is maintained during pmic reset.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ regulator-name: true
+ regulator-boot-on: true
+ regulator-always-on: true
+ regulator-min-microvolt: true
+ regulator-max-microvolt: true
+ regulator-allow-bypass: true
+ regulator-over-current-protection: true
+
+ additionalProperties: false
+
+ ldo4:
+ type: object
+
+ properties:
+ interrupts:
+ maxItems: 1
+
+ st,mask-reset:
+ description: mask reset for this regulator,
+ the regulator configuration is maintained during pmic reset.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ regulator-name: true
+ regulator-boot-on: true
+ regulator-always-on: true
+ regulator-over-current-protection: true
+
+ additionalProperties: false
+
+ vref_ddr:
+ type: object
+
+ properties:
+ interrupts:
+ maxItems: 1
+
+ st,mask-reset:
+ description: mask reset for this regulator,
+ the regulator configuration is maintained during pmic reset.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ regulator-name: true
+ regulator-boot-on: true
+ regulator-always-on: true
+
+ additionalProperties: false
+
+ boost:
+ type: object
+
+ properties:
+ interrupts:
+ maxItems: 1
+
+ st,mask-reset:
+ description: mask reset for this regulator,
+ the regulator configuration is maintained during pmic reset.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ regulator-name: true
+ regulator-boot-on: true
+ regulator-always-on: true
+ regulator-over-current-protection: true
+
+ additionalProperties: false
+
+ patternProperties:
+ "^(buck[1-4]|ldo[1-6]|boost|pwr_sw[1-2])-supply$":
+ description: STPMIC1 voltage regulators supplies
+
+ "^(buck[1-4]|ldo[1-6]|boost|vref_ddr|pwr_sw[1-2])$":
+ allOf:
+ - $ref: ../regulator/regulator.yaml
+
+ "^ldo[1-2,5-6]$":
+ type: object
+
+ properties:
+ interrupts:
+ maxItems: 1
+
+ st,mask-reset:
+ description: mask reset for this regulator,
+ the regulator configuration is maintained during pmic reset.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ regulator-name: true
+ regulator-boot-on: true
+ regulator-always-on: true
+ regulator-min-microvolt: true
+ regulator-max-microvolt: true
+ regulator-over-current-protection: true
+ regulator-enable-ramp-delay: true
+
+ additionalProperties: false
+
+ "^buck[1-4]$":
+ type: object
+
+ properties:
+ interrupts:
+ maxItems: 1
+
+ st,mask-reset:
+ description: mask reset for this regulator,
+ the regulator configuration is maintained during pmic reset.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ regulator-name: true
+ regulator-boot-on: true
+ regulator-always-on: true
+ regulator-min-microvolt: true
+ regulator-max-microvolt: true
+ regulator-initial-mode: true
+ regulator-pull-down: true
+ regulator-over-current-protection: true
+ regulator-enable-ramp-delay: true
+
+ additionalProperties: false
+
+ "^pwr_sw[1-2]$":
+ type: object
+
+ properties:
+ interrupts:
+ maxItems: 1
+
+ regulator-name: true
+ regulator-boot-on: true
+ regulator-always-on: true
+ regulator-over-current-protection: true
+ regulator-active-discharge: true
+
+ additionalProperties: false
+
+ required:
+ - compatible
+
+ additionalProperties: false
+
+ additionalProperties: false
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#interrupt-cells"
+ - interrupt-controller
+
+examples:
+ - |
+ #include <dt-bindings/mfd/st,stpmic1.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pmic@33 {
+ compatible = "st,stpmic1";
+ reg = <0x33>;
+ interrupt-parent = <&gpioa>;
+ interrupts = <0 2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ onkey {
+ compatible = "st,stpmic1-onkey";
+ interrupts = <IT_PONKEY_F 0>,<IT_PONKEY_R 1>;
+ interrupt-names = "onkey-falling", "onkey-rising";
+ power-off-time-sec = <10>;
+ };
+
+ watchdog {
+ compatible = "st,stpmic1-wdt";
+ };
+
+ regulators {
+ compatible = "st,stpmic1-regulators";
+
+ ldo6-supply = <&v3v3>;
+
+ buck1 {
+ regulator-name = "vdd_core";
+ interrupts = <IT_CURLIM_BUCK1 0>;
+ st,mask-reset;
+ regulator-boot-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ buck3 {
+ regulator-name = "vdd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-pull-down;
+ };
+
+ buck4 {
+ regulator-name = "v3v3";
+ interrupts = <IT_CURLIM_BUCK4 0>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo6 {
+ regulator-name = "v1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-over-current-protection;
+ };
+ };
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml b/Documentation/devicetree/bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml
index 0ea21a6f70b4..38ab0499102d 100644
--- a/Documentation/devicetree/bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml
+++ b/Documentation/devicetree/bindings/misc/intel,ixp4xx-ahb-queue-manager.yaml
@@ -38,6 +38,8 @@ required:
- reg
- interrupts
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
new file mode 100644
index 000000000000..2f45dd0d04db
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
+
+maintainers:
+ - Masahiro Yamada <yamada.masahiro@socionext.com>
+ - Piotr Sroka <piotrs@cadence.com>
+
+allOf:
+ - $ref: mmc-controller.yaml
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - socionext,uniphier-sd4hc
+ - const: cdns,sd4hc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ # PHY DLL input delays:
+ # They are used to delay the data valid window, and align the window to
+ # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
+ # and it is increased by 2.5ns in each step.
+
+ cdns,phy-input-delay-sd-highspeed:
+ description: Value of the delay in the input path for SD high-speed timing
+ allOf:
+ - $ref: "/schemas/types.yaml#/definitions/uint32"
+ - minimum: 0
+ - maximum: 0x1f
+
+ cdns,phy-input-delay-legacy:
+ description: Value of the delay in the input path for legacy timing
+ allOf:
+ - $ref: "/schemas/types.yaml#/definitions/uint32"
+ - minimum: 0
+ - maximum: 0x1f
+
+ cdns,phy-input-delay-sd-uhs-sdr12:
+ description: Value of the delay in the input path for SD UHS SDR12 timing
+ allOf:
+ - $ref: "/schemas/types.yaml#/definitions/uint32"
+ - minimum: 0
+ - maximum: 0x1f
+
+ cdns,phy-input-delay-sd-uhs-sdr25:
+ description: Value of the delay in the input path for SD UHS SDR25 timing
+ allOf:
+ - $ref: "/schemas/types.yaml#/definitions/uint32"
+ - minimum: 0
+ - maximum: 0x1f
+
+ cdns,phy-input-delay-sd-uhs-sdr50:
+ description: Value of the delay in the input path for SD UHS SDR50 timing
+ allOf:
+ - $ref: "/schemas/types.yaml#/definitions/uint32"
+ - minimum: 0
+ - maximum: 0x1f
+
+ cdns,phy-input-delay-sd-uhs-ddr50:
+ description: Value of the delay in the input path for SD UHS DDR50 timing
+ allOf:
+ - $ref: "/schemas/types.yaml#/definitions/uint32"
+ - minimum: 0
+ - maximum: 0x1f
+
+ cdns,phy-input-delay-mmc-highspeed:
+ description: Value of the delay in the input path for MMC high-speed timing
+ allOf:
+ - $ref: "/schemas/types.yaml#/definitions/uint32"
+ - minimum: 0
+ - maximum: 0x1f
+
+ cdns,phy-input-delay-mmc-ddr:
+ description: Value of the delay in the input path for eMMC high-speed DDR timing
+ allOf:
+ - $ref: "/schemas/types.yaml#/definitions/uint32"
+ - minimum: 0
+ - maximum: 0x1f
+
+ # PHY DLL clock delays:
+ # Each delay property represents the fraction of the clock period.
+ # The approximate delay value will be
+ # (<delay property value>/128)*sdmclk_clock_period.
+
+ cdns,phy-dll-delay-sdclk:
+ description: |
+ Value of the delay introduced on the sdclk output for all modes except
+ HS200, HS400 and HS400_ES.
+ allOf:
+ - $ref: "/schemas/types.yaml#/definitions/uint32"
+ - minimum: 0
+ - maximum: 0x7f
+
+ cdns,phy-dll-delay-sdclk-hsmmc:
+ description: |
+ Value of the delay introduced on the sdclk output for HS200, HS400 and
+ HS400_ES speed modes.
+ allOf:
+ - $ref: "/schemas/types.yaml#/definitions/uint32"
+ - minimum: 0
+ - maximum: 0x7f
+
+ cdns,phy-dll-delay-strobe:
+ description: |
+ Value of the delay introduced on the dat_strobe input used in
+ HS400 / HS400_ES speed modes.
+ allOf:
+ - $ref: "/schemas/types.yaml#/definitions/uint32"
+ - minimum: 0
+ - maximum: 0x7f
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+examples:
+ - |
+ emmc: mmc@5a000000 {
+ compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
+ reg = <0x5a000000 0x400>;
+ interrupts = <0 78 4>;
+ clocks = <&clk 4>;
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ cdns,phy-dll-delay-sdclk = <0>;
+ };
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt b/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt
deleted file mode 100644
index fa423c277853..000000000000
--- a/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt
+++ /dev/null
@@ -1,80 +0,0 @@
-* Cadence SD/SDIO/eMMC Host Controller
-
-Required properties:
-- compatible: should be one of the following:
- "cdns,sd4hc" - default of the IP
- "socionext,uniphier-sd4hc" - for Socionext UniPhier SoCs
-- reg: offset and length of the register set for the device.
-- interrupts: a single interrupt specifier.
-- clocks: phandle to the input clock.
-
-Optional properties:
-For eMMC configuration, supported speed modes are not indicated by the SDHCI
-Capabilities Register. Instead, the following properties should be specified
-if supported. See mmc.txt for details.
-- mmc-ddr-1_8v
-- mmc-ddr-1_2v
-- mmc-hs200-1_8v
-- mmc-hs200-1_2v
-- mmc-hs400-1_8v
-- mmc-hs400-1_2v
-
-Some PHY delays can be configured by following properties.
-PHY DLL input delays:
-They are used to delay the data valid window, and align the window
-to sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
-and it is increased by 2.5ns in each step.
-- cdns,phy-input-delay-sd-highspeed:
- Value of the delay in the input path for SD high-speed timing
- Valid range = [0:0x1F].
-- cdns,phy-input-delay-legacy:
- Value of the delay in the input path for legacy timing
- Valid range = [0:0x1F].
-- cdns,phy-input-delay-sd-uhs-sdr12:
- Value of the delay in the input path for SD UHS SDR12 timing
- Valid range = [0:0x1F].
-- cdns,phy-input-delay-sd-uhs-sdr25:
- Value of the delay in the input path for SD UHS SDR25 timing
- Valid range = [0:0x1F].
-- cdns,phy-input-delay-sd-uhs-sdr50:
- Value of the delay in the input path for SD UHS SDR50 timing
- Valid range = [0:0x1F].
-- cdns,phy-input-delay-sd-uhs-ddr50:
- Value of the delay in the input path for SD UHS DDR50 timing
- Valid range = [0:0x1F].
-- cdns,phy-input-delay-mmc-highspeed:
- Value of the delay in the input path for MMC high-speed timing
- Valid range = [0:0x1F].
-- cdns,phy-input-delay-mmc-ddr:
- Value of the delay in the input path for eMMC high-speed DDR timing
- Valid range = [0:0x1F].
-
-PHY DLL clock delays:
-Each delay property represents the fraction of the clock period.
-The approximate delay value will be
-(<delay property value>/128)*sdmclk_clock_period.
-- cdns,phy-dll-delay-sdclk:
- Value of the delay introduced on the sdclk output
- for all modes except HS200, HS400 and HS400_ES.
- Valid range = [0:0x7F].
-- cdns,phy-dll-delay-sdclk-hsmmc:
- Value of the delay introduced on the sdclk output
- for HS200, HS400 and HS400_ES speed modes.
- Valid range = [0:0x7F].
-- cdns,phy-dll-delay-strobe:
- Value of the delay introduced on the dat_strobe input
- used in HS400 / HS400_ES speed modes.
- Valid range = [0:0x7F].
-
-Example:
- emmc: sdhci@5a000000 {
- compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
- reg = <0x5a000000 0x400>;
- interrupts = <0 78 4>;
- clocks = <&clk 4>;
- bus-width = <8>;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
- mmc-hs400-1_8v;
- cdns,phy-dll-delay-sdclk = <0>;
- };
diff --git a/Documentation/devicetree/bindings/mmc/socionext,uniphier-sd.yaml b/Documentation/devicetree/bindings/mmc/socionext,uniphier-sd.yaml
new file mode 100644
index 000000000000..cdfac9b4411b
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/socionext,uniphier-sd.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/socionext,uniphier-sd.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UniPhier SD/SDIO/eMMC controller
+
+maintainers:
+ - Masahiro Yamada <yamada.masahiro@socionext.com>
+
+properties:
+ compatible:
+ description: version 2.91, 3.1, 3.1.1, respectively
+ enum:
+ - socionext,uniphier-sd-v2.91
+ - socionext,uniphier-sd-v3.1
+ - socionext,uniphier-sd-v3.1.1
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ reset-names:
+ description: |
+ There are three reset signals at maximum
+ host: mandatory for all variants
+ bridge: exist only for version 2.91
+ hw: optional. exist if eMMC hw reset line is available
+ oneOf:
+ - const: host
+ - items:
+ - const: host
+ - const: bridge
+ - items:
+ - const: host
+ - const: hw
+ - items:
+ - const: host
+ - const: bridge
+ - const: hw
+
+ resets:
+ minItems: 1
+ maxItems: 3
+
+allOf:
+ - $ref: mmc-controller.yaml
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: socionext,uniphier-sd-v2.91
+ then:
+ properties:
+ reset-names:
+ contains:
+ const: bridge
+ else:
+ properties:
+ reset-names:
+ not:
+ contains:
+ const: bridge
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - reset-names
+ - resets
+
+examples:
+ - |
+ sd: mmc@5a400000 {
+ compatible = "socionext,uniphier-sd-v2.91";
+ reg = <0x5a400000 0x200>;
+ interrupts = <0 76 4>;
+ pinctrl-names = "default", "uhs";
+ pinctrl-0 = <&pinctrl_sd>;
+ pinctrl-1 = <&pinctrl_sd_uhs>;
+ clocks = <&mio_clk 0>;
+ reset-names = "host", "bridge";
+ resets = <&mio_rst 0>, <&mio_rst 3>;
+ dma-names = "rx-tx";
+ dmas = <&dmac 4>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ };
diff --git a/Documentation/devicetree/bindings/mmc/uniphier-sd.txt b/Documentation/devicetree/bindings/mmc/uniphier-sd.txt
deleted file mode 100644
index e1d658755722..000000000000
--- a/Documentation/devicetree/bindings/mmc/uniphier-sd.txt
+++ /dev/null
@@ -1,55 +0,0 @@
-UniPhier SD/eMMC controller
-
-Required properties:
-- compatible: should be one of the following:
- "socionext,uniphier-sd-v2.91" - IP version 2.91
- "socionext,uniphier-sd-v3.1" - IP version 3.1
- "socionext,uniphier-sd-v3.1.1" - IP version 3.1.1
-- reg: offset and length of the register set for the device.
-- interrupts: a single interrupt specifier.
-- clocks: a single clock specifier of the controller clock.
-- reset-names: should contain the following:
- "host" - mandatory for all versions
- "bridge" - should exist only for "socionext,uniphier-sd-v2.91"
- "hw" - should exist if eMMC hw reset line is available
-- resets: a list of reset specifiers, corresponding to the reset-names
-
-Optional properties:
-- pinctrl-names: if present, should contain the following:
- "default" - should exist for all instances
- "uhs" - should exist for SD instance with UHS support
-- pinctrl-0: pin control state for the default mode
-- pinctrl-1: pin control state for the UHS mode
-- dma-names: should be "rx-tx" if present.
- This property can exist only for "socionext,uniphier-sd-v2.91".
-- dmas: a single DMA channel specifier
- This property can exist only for "socionext,uniphier-sd-v2.91".
-- bus-width: see mmc.txt
-- cap-sd-highspeed: see mmc.txt
-- cap-mmc-highspeed: see mmc.txt
-- sd-uhs-sdr12: see mmc.txt
-- sd-uhs-sdr25: see mmc.txt
-- sd-uhs-sdr50: see mmc.txt
-- cap-mmc-hw-reset: should exist if reset-names contains "hw". see mmc.txt
-- non-removable: see mmc.txt
-
-Example:
-
- sd: sdhc@5a400000 {
- compatible = "socionext,uniphier-sd-v2.91";
- reg = <0x5a400000 0x200>;
- interrupts = <0 76 4>;
- pinctrl-names = "default", "uhs";
- pinctrl-0 = <&pinctrl_sd>;
- pinctrl-1 = <&pinctrl_sd_uhs>;
- clocks = <&mio_clk 0>;
- reset-names = "host", "bridge";
- resets = <&mio_rst 0>, <&mio_rst 3>;
- dma-names = "rx-tx";
- dmas = <&dmac 4>;
- bus-width = <4>;
- cap-sd-highspeed;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- };
diff --git a/Documentation/devicetree/bindings/mtd/denali,nand.yaml b/Documentation/devicetree/bindings/mtd/denali,nand.yaml
new file mode 100644
index 000000000000..46e6b6726bc0
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/denali,nand.yaml
@@ -0,0 +1,148 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/denali,nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Denali NAND controller
+
+maintainers:
+ - Masahiro Yamada <yamada.masahiro@socionext.com>
+
+properties:
+ compatible:
+ enum:
+ - altr,socfpga-denali-nand
+ - socionext,uniphier-denali-nand-v5a
+ - socionext,uniphier-denali-nand-v5b
+
+ reg-names:
+ description: |
+ There are two register regions:
+ nand_data: host data/command interface
+ denali_reg: register interface
+ items:
+ - const: nand_data
+ - const: denali_reg
+
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ interrupts:
+ maxItems: 1
+
+ clock-names:
+ description: |
+ There are three clocks:
+ nand: controller core clock
+ nand_x: bus interface clock
+ ecc: ECC circuit clock
+ items:
+ - const: nand
+ - const: nand_x
+ - const: ecc
+
+ clocks:
+ minItems: 3
+ maxItems: 3
+
+ reset-names:
+ description: |
+ There are two optional resets:
+ nand: controller core reset
+ reg: register reset
+ oneOf:
+ - items:
+ - const: nand
+ - const: reg
+ - const: nand
+ - const: reg
+
+ resets:
+ minItems: 1
+ maxItems: 2
+
+allOf:
+ - $ref: nand-controller.yaml
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: altr,socfpga-denali-nand
+ then:
+ patternProperties:
+ "^nand@[a-f0-9]$":
+ type: object
+ properties:
+ nand-ecc-strength:
+ enum:
+ - 8
+ - 15
+ nand-ecc-step-size:
+ enum:
+ - 512
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: socionext,uniphier-denali-nand-v5a
+ then:
+ patternProperties:
+ "^nand@[a-f0-9]$":
+ type: object
+ properties:
+ nand-ecc-strength:
+ enum:
+ - 8
+ - 16
+ - 24
+ nand-ecc-step-size:
+ enum:
+ - 1024
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: socionext,uniphier-denali-nand-v5b
+ then:
+ patternProperties:
+ "^nand@[a-f0-9]$":
+ type: object
+ properties:
+ nand-ecc-strength:
+ enum:
+ - 8
+ - 16
+ nand-ecc-step-size:
+ enum:
+ - 1024
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clock-names
+ - clocks
+
+examples:
+ - |
+ nand-controller@ff900000 {
+ compatible = "altr,socfpga-denali-nand";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0xff900000 0x20>, <0xffb80000 0x1000>;
+ interrupts = <0 144 4>;
+ clock-names = "nand", "nand_x", "ecc";
+ clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
+ reset-names = "nand", "reg";
+ resets = <&nand_rst>, <&nand_reg_rst>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt b/Documentation/devicetree/bindings/mtd/denali-nand.txt
deleted file mode 100644
index 98916a84bbf6..000000000000
--- a/Documentation/devicetree/bindings/mtd/denali-nand.txt
+++ /dev/null
@@ -1,61 +0,0 @@
-* Denali NAND controller
-
-Required properties:
- - compatible : should be one of the following:
- "altr,socfpga-denali-nand" - for Altera SOCFPGA
- "socionext,uniphier-denali-nand-v5a" - for Socionext UniPhier (v5a)
- "socionext,uniphier-denali-nand-v5b" - for Socionext UniPhier (v5b)
- - reg : should contain registers location and length for data and reg.
- - reg-names: Should contain the reg names "nand_data" and "denali_reg"
- - #address-cells: should be 1. The cell encodes the chip select connection.
- - #size-cells : should be 0.
- - interrupts : The interrupt number.
- - clocks: should contain phandle of the controller core clock, the bus
- interface clock, and the ECC circuit clock.
- - clock-names: should contain "nand", "nand_x", "ecc"
-
-Optional properties:
- - resets: may contain phandles to the controller core reset, the register
- reset
- - reset-names: may contain "nand", "reg"
-
-Sub-nodes:
- Sub-nodes represent available NAND chips.
-
- Required properties:
- - reg: should contain the bank ID of the controller to which each chip
- select is connected.
-
- Optional properties:
- - nand-ecc-step-size: see nand-controller.yaml for details.
- If present, the value must be
- 512 for "altr,socfpga-denali-nand"
- 1024 for "socionext,uniphier-denali-nand-v5a"
- 1024 for "socionext,uniphier-denali-nand-v5b"
- - nand-ecc-strength: see nand-controller.yaml for details. Valid values are:
- 8, 15 for "altr,socfpga-denali-nand"
- 8, 16, 24 for "socionext,uniphier-denali-nand-v5a"
- 8, 16 for "socionext,uniphier-denali-nand-v5b"
- - nand-ecc-maximize: see nand-controller.yaml for details
-
-The chip nodes may optionally contain sub-nodes describing partitions of the
-address space. See partition.txt for more detail.
-
-Examples:
-
-nand: nand@ff900000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "altr,socfpga-denali-nand";
- reg = <0xff900000 0x20>, <0xffb80000 0x1000>;
- reg-names = "nand_data", "denali_reg";
- clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
- clock-names = "nand", "nand_x", "ecc";
- resets = <&nand_rst>, <&nand_reg_rst>;
- reset-names = "nand", "reg";
- interrupts = <0 144 4>;
-
- nand@0 {
- reg = <0>;
- }
-};
diff --git a/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt b/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt
index dd258674633c..a7d57ba5f2ac 100644
--- a/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt
+++ b/Documentation/devicetree/bindings/net/broadcom-bluetooth.txt
@@ -20,7 +20,7 @@ Required properties:
Optional properties:
- - max-speed: see Documentation/devicetree/bindings/serial/slave-device.txt
+ - max-speed: see Documentation/devicetree/bindings/serial/serial.yaml
- shutdown-gpios: GPIO specifier, used to enable the BT module
- device-wakeup-gpios: GPIO specifier, used to wakeup the controller
- host-wakeup-gpios: GPIO specifier, used to wakeup the host processor.
diff --git a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml
new file mode 100644
index 000000000000..cccf8202c8f7
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/can/bosch,m_can.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bosch MCAN controller Bindings
+
+description: Bosch MCAN controller for CAN bus
+
+maintainers:
+ - Sriram Dash <sriram.dash@samsung.com>
+
+properties:
+ compatible:
+ const: bosch,m_can
+
+ reg:
+ items:
+ - description: M_CAN registers map
+ - description: message RAM
+
+ reg-names:
+ items:
+ - const: m_can
+ - const: message_ram
+
+ interrupts:
+ items:
+ - description: interrupt line0
+ - description: interrupt line1
+ minItems: 1
+ maxItems: 2
+
+ interrupt-names:
+ items:
+ - const: int0
+ - const: int1
+ minItems: 1
+ maxItems: 2
+
+ clocks:
+ items:
+ - description: peripheral clock
+ - description: bus clock
+
+ clock-names:
+ items:
+ - const: hclk
+ - const: cclk
+
+ bosch,mram-cfg:
+ description: |
+ Message RAM configuration data.
+ Multiple M_CAN instances can share the same Message RAM
+ and each element(e.g Rx FIFO or Tx Buffer and etc) number
+ in Message RAM is also configurable, so this property is
+ telling driver how the shared or private Message RAM are
+ used by this M_CAN controller.
+
+ The format should be as follows:
+ <offset sidf_elems xidf_elems rxf0_elems rxf1_elems rxb_elems txe_elems txb_elems>
+ The 'offset' is an address offset of the Message RAM where
+ the following elements start from. This is usually set to
+ 0x0 if you're using a private Message RAM. The remain cells
+ are used to specify how many elements are used for each FIFO/Buffer.
+
+ M_CAN includes the following elements according to user manual:
+ 11-bit Filter 0-128 elements / 0-128 words
+ 29-bit Filter 0-64 elements / 0-128 words
+ Rx FIFO 0 0-64 elements / 0-1152 words
+ Rx FIFO 1 0-64 elements / 0-1152 words
+ Rx Buffers 0-64 elements / 0-1152 words
+ Tx Event FIFO 0-32 elements / 0-64 words
+ Tx Buffers 0-32 elements / 0-576 words
+
+ Please refer to 2.4.1 Message RAM Configuration in Bosch
+ M_CAN user manual for details.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/int32-array
+ - items:
+ items:
+ - description: The 'offset' is an address offset of the Message RAM
+ where the following elements start from. This is usually
+ set to 0x0 if you're using a private Message RAM.
+ default: 0
+ - description: 11-bit Filter 0-128 elements / 0-128 words
+ minimum: 0
+ maximum: 128
+ - description: 29-bit Filter 0-64 elements / 0-128 words
+ minimum: 0
+ maximum: 64
+ - description: Rx FIFO 0 0-64 elements / 0-1152 words
+ minimum: 0
+ maximum: 64
+ - description: Rx FIFO 1 0-64 elements / 0-1152 words
+ minimum: 0
+ maximum: 64
+ - description: Rx Buffers 0-64 elements / 0-1152 words
+ minimum: 0
+ maximum: 64
+ - description: Tx Event FIFO 0-32 elements / 0-64 words
+ minimum: 0
+ maximum: 32
+ - description: Tx Buffers 0-32 elements / 0-576 words
+ minimum: 0
+ maximum: 32
+ maxItems: 1
+
+ can-transceiver:
+ $ref: can-transceiver.yaml#
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - bosch,mram-cfg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx6sx-clock.h>
+ can@20e8000 {
+ compatible = "bosch,m_can";
+ reg = <0x020e8000 0x4000>, <0x02298000 0x4000>;
+ reg-names = "m_can", "message_ram";
+ interrupts = <0 114 0x04>, <0 114 0x04>;
+ interrupt-names = "int0", "int1";
+ clocks = <&clks IMX6SX_CLK_CANFD>,
+ <&clks IMX6SX_CLK_CANFD>;
+ clock-names = "hclk", "cclk";
+ bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>;
+
+ can-transceiver {
+ max-bitrate = <5000000>;
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/net/can/can-transceiver.txt b/Documentation/devicetree/bindings/net/can/can-transceiver.txt
deleted file mode 100644
index 0011f53ff159..000000000000
--- a/Documentation/devicetree/bindings/net/can/can-transceiver.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-Generic CAN transceiver Device Tree binding
-------------------------------
-
-CAN transceiver typically limits the max speed in standard CAN and CAN FD
-modes. Typically these limitations are static and the transceivers themselves
-provide no way to detect this limitation at runtime. For this situation,
-the "can-transceiver" node can be used.
-
-Required Properties:
- max-bitrate: a positive non 0 value that determines the max
- speed that CAN/CAN-FD can run. Any other value
- will be ignored.
-
-Examples:
-
-Based on Texas Instrument's TCAN1042HGV CAN Transceiver
-
-m_can0 {
- ....
- can-transceiver {
- max-bitrate = <5000000>;
- };
- ...
-};
diff --git a/Documentation/devicetree/bindings/net/can/can-transceiver.yaml b/Documentation/devicetree/bindings/net/can/can-transceiver.yaml
new file mode 100644
index 000000000000..6396977d29e5
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/can/can-transceiver.yaml
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/can/can-transceiver.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: CAN transceiver Bindings
+
+description: CAN transceiver generic properties bindings
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+
+properties:
+ max-bitrate:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: a positive non 0 value that determines the max speed that CAN/CAN-FD can run.
+ minimum: 1
diff --git a/Documentation/devicetree/bindings/net/can/m_can.txt b/Documentation/devicetree/bindings/net/can/m_can.txt
deleted file mode 100644
index ed614383af9c..000000000000
--- a/Documentation/devicetree/bindings/net/can/m_can.txt
+++ /dev/null
@@ -1,75 +0,0 @@
-Bosch MCAN controller Device Tree Bindings
--------------------------------------------------
-
-Required properties:
-- compatible : Should be "bosch,m_can" for M_CAN controllers
-- reg : physical base address and size of the M_CAN
- registers map and Message RAM
-- reg-names : Should be "m_can" and "message_ram"
-- interrupts : Should be the interrupt number of M_CAN interrupt
- line 0 and line 1, could be same if sharing
- the same interrupt.
-- interrupt-names : Should contain "int0" and "int1"
-- clocks : Clocks used by controller, should be host clock
- and CAN clock.
-- clock-names : Should contain "hclk" and "cclk"
-- pinctrl-<n> : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt
-- pinctrl-names : Names corresponding to the numbered pinctrl states
-- bosch,mram-cfg : Message RAM configuration data.
- Multiple M_CAN instances can share the same Message
- RAM and each element(e.g Rx FIFO or Tx Buffer and etc)
- number in Message RAM is also configurable,
- so this property is telling driver how the shared or
- private Message RAM are used by this M_CAN controller.
-
- The format should be as follows:
- <offset sidf_elems xidf_elems rxf0_elems rxf1_elems
- rxb_elems txe_elems txb_elems>
- The 'offset' is an address offset of the Message RAM
- where the following elements start from. This is
- usually set to 0x0 if you're using a private Message
- RAM. The remain cells are used to specify how many
- elements are used for each FIFO/Buffer.
-
- M_CAN includes the following elements according to user manual:
- 11-bit Filter 0-128 elements / 0-128 words
- 29-bit Filter 0-64 elements / 0-128 words
- Rx FIFO 0 0-64 elements / 0-1152 words
- Rx FIFO 1 0-64 elements / 0-1152 words
- Rx Buffers 0-64 elements / 0-1152 words
- Tx Event FIFO 0-32 elements / 0-64 words
- Tx Buffers 0-32 elements / 0-576 words
-
- Please refer to 2.4.1 Message RAM Configuration in
- Bosch M_CAN user manual for details.
-
-Optional Subnode:
-- can-transceiver : Can-transceiver subnode describing maximum speed
- that can be used for CAN/CAN-FD modes. See
- Documentation/devicetree/bindings/net/can/can-transceiver.txt
- for details.
-Example:
-SoC dtsi:
-m_can1: can@20e8000 {
- compatible = "bosch,m_can";
- reg = <0x020e8000 0x4000>, <0x02298000 0x4000>;
- reg-names = "m_can", "message_ram";
- interrupts = <0 114 0x04>,
- <0 114 0x04>;
- interrupt-names = "int0", "int1";
- clocks = <&clks IMX6SX_CLK_CANFD>,
- <&clks IMX6SX_CLK_CANFD>;
- clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>;
-};
-
-Board dts:
-&m_can1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_m_can1>;
- status = "enabled";
-
- can-transceiver {
- max-bitrate = <5000000>;
- };
-};
diff --git a/Documentation/devicetree/bindings/net/can/tcan4x5x.txt b/Documentation/devicetree/bindings/net/can/tcan4x5x.txt
index 6bdcc3f84bd3..3613c2c8f75d 100644
--- a/Documentation/devicetree/bindings/net/can/tcan4x5x.txt
+++ b/Documentation/devicetree/bindings/net/can/tcan4x5x.txt
@@ -14,7 +14,7 @@ Required properties:
the interrupt.
- interrupts: interrupt specification for data-ready.
-See Documentation/devicetree/bindings/net/can/m_can.txt for additional
+See Documentation/devicetree/bindings/net/can/bosch,m_can.yaml for additional
required property details.
Optional properties:
diff --git a/Documentation/devicetree/bindings/net/mediatek-bluetooth.txt b/Documentation/devicetree/bindings/net/mediatek-bluetooth.txt
index 112011c51d5e..219bcbd0d344 100644
--- a/Documentation/devicetree/bindings/net/mediatek-bluetooth.txt
+++ b/Documentation/devicetree/bindings/net/mediatek-bluetooth.txt
@@ -42,7 +42,7 @@ child node of the serial node with UART.
Please refer to the following documents for generic properties:
- Documentation/devicetree/bindings/serial/slave-device.txt
+ Documentation/devicetree/bindings/serial/serial.yaml
Required properties:
diff --git a/Documentation/devicetree/bindings/net/qca,qca7000.txt b/Documentation/devicetree/bindings/net/qca,qca7000.txt
index 21c36e524993..8f5ae0b84eec 100644
--- a/Documentation/devicetree/bindings/net/qca,qca7000.txt
+++ b/Documentation/devicetree/bindings/net/qca,qca7000.txt
@@ -68,7 +68,7 @@ Required properties:
Optional properties:
- local-mac-address : see ./ethernet.txt
- current-speed : current baud rate of QCA7000 which defaults to 115200
- if absent, see also ../serial/slave-device.txt
+ if absent, see also ../serial/serial.yaml
UART Example:
diff --git a/Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml b/Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml
index ac8c76369a86..976f139bb66e 100644
--- a/Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml
+++ b/Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml
@@ -37,6 +37,12 @@ properties:
description:
The physical base address and size of full the CPSW module IO range
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
ranges: true
clocks:
@@ -111,13 +117,6 @@ properties:
- reg
- phys
- mdio:
- type: object
- allOf:
- - $ref: "ti,davinci-mdio.yaml#"
- description:
- CPSW MDIO bus.
-
cpts:
type: object
description:
@@ -148,6 +147,15 @@ properties:
- clocks
- clock-names
+patternProperties:
+ "^mdio@":
+ type: object
+ allOf:
+ - $ref: "ti,davinci-mdio.yaml#"
+ description:
+ CPSW MDIO bus.
+
+
required:
- compatible
- reg
@@ -159,6 +167,8 @@ required:
- '#address-cells'
- '#size-cells'
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
@@ -174,7 +184,6 @@ examples:
#address-cells = <1>;
#size-cells = <1>;
syscon = <&scm_conf>;
- inctrl-names = "default", "sleep";
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/Documentation/devicetree/bindings/net/ti-bluetooth.txt b/Documentation/devicetree/bindings/net/ti-bluetooth.txt
index 6d03ff8c7068..f48c17b38f58 100644
--- a/Documentation/devicetree/bindings/net/ti-bluetooth.txt
+++ b/Documentation/devicetree/bindings/net/ti-bluetooth.txt
@@ -15,8 +15,7 @@ standard BT HCI protocol with additional channels for the other functions.
TI WiLink devices also have a separate WiFi interface as described in
wireless/ti,wlcore.txt.
-This bindings follows the UART slave device binding in
-../serial/slave-device.txt.
+This bindings follows the UART slave device binding in ../serial/serial.yaml.
Required properties:
- compatible: should be one of the following:
diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun50i-h6-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun50i-h6-usb3-phy.yaml
index e5922b427342..c03b83103e87 100644
--- a/Documentation/devicetree/bindings/phy/allwinner,sun50i-h6-usb3-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/allwinner,sun50i-h6-usb3-phy.yaml
@@ -34,6 +34,8 @@ required:
- resets
- "#phy-cells"
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/sun50i-h6-ccu.h>
diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml
index 346f9c35427c..453c083cf44c 100644
--- a/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml
@@ -44,6 +44,8 @@ required:
- reset-names
- "#phy-cells"
+additionalProperties: false
+
examples:
- |
phy@46000 {
diff --git a/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml b/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml
index 0ccee64c6962..9a346d6290d9 100644
--- a/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml
@@ -40,6 +40,8 @@ required:
- reg
- clocks
+additionalProperties: false
+
examples:
- |
sysconf: chiptop@e0200000 {
diff --git a/Documentation/devicetree/bindings/phy/marvell,mmp3-hsic-phy.yaml b/Documentation/devicetree/bindings/phy/marvell,mmp3-hsic-phy.yaml
index 5ab436189f3b..00609ace677c 100644
--- a/Documentation/devicetree/bindings/phy/marvell,mmp3-hsic-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/marvell,mmp3-hsic-phy.yaml
@@ -31,6 +31,8 @@ required:
- reset-gpios
- "#phy-cells"
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/gpio/gpio.h>
diff --git a/Documentation/devicetree/bindings/phy/marvell,mmp3-usb-phy.yaml b/Documentation/devicetree/bindings/phy/marvell,mmp3-usb-phy.yaml
new file mode 100644
index 000000000000..c97043eaa8fb
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/marvell,mmp3-usb-phy.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+# Copyright 2019,2020 Lubomir Rintel <lkundrak@v3.sk>
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/marvell,mmp3-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell MMP3 USB PHY bindings
+
+maintainers:
+ - Lubomir Rintel <lkundrak@v3.sk>
+
+properties:
+ $nodename:
+ pattern: '^usb-phy@[a-f0-9]+$'
+
+ compatible:
+ const: marvell,mmp3-usb-phy
+
+ reg:
+ maxItems: 1
+ description: base address of the device
+
+ '#phy-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - '#phy-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ usb-phy@d4207000 {
+ compatible = "marvell,mmp3-usb-phy";
+ reg = <0xd4207000 0x40>;
+ #phy-cells = <0>;
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/phy/phy-mmp3-usb.txt b/Documentation/devicetree/bindings/phy/phy-mmp3-usb.txt
deleted file mode 100644
index 7183b9102f91..000000000000
--- a/Documentation/devicetree/bindings/phy/phy-mmp3-usb.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-Marvell MMP3 USB PHY
---------------------
-
-Required properties:
-- compatible: must be "marvell,mmp3-usb-phy"
-- #phy-cells: must be 0
-
-Example:
- usb-phy: usb-phy@d4207000 {
- compatible = "marvell,mmp3-usb-phy";
- reg = <0xd4207000 0x40>;
- #phy-cells = <0>;
- };
diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
deleted file mode 100644
index 541f5298827c..000000000000
--- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
+++ /dev/null
@@ -1,81 +0,0 @@
-ROCKCHIP USB2.0 PHY WITH INNO IP BLOCK
-
-Required properties (phy (parent) node):
- - compatible : should be one of the listed compatibles:
- * "rockchip,px30-usb2phy"
- * "rockchip,rk3228-usb2phy"
- * "rockchip,rk3328-usb2phy"
- * "rockchip,rk3366-usb2phy"
- * "rockchip,rk3399-usb2phy"
- * "rockchip,rv1108-usb2phy"
- - reg : the address offset of grf for usb-phy configuration.
- - #clock-cells : should be 0.
- - clock-output-names : specify the 480m output clock name.
-
-Optional properties:
- - clocks : phandle + phy specifier pair, for the input clock of phy.
- - clock-names : input clock name of phy, must be "phyclk".
- - assigned-clocks : phandle of usb 480m clock.
- - assigned-clock-parents : parent of usb 480m clock, select between
- usb-phy output 480m and xin24m.
- Refer to clk/clock-bindings.txt for generic clock
- consumer properties.
- - rockchip,usbgrf : phandle to the syscon managing the "usb general
- register files". When set driver will request its
- phandle as one companion-grf for some special SoCs
- (e.g RV1108).
- - extcon : phandle to the extcon device providing the cable state for
- the otg phy.
-
-Required nodes : a sub-node is required for each port the phy provides.
- The sub-node name is used to identify host or otg port,
- and shall be the following entries:
- * "otg-port" : the name of otg port.
- * "host-port" : the name of host port.
-
-Required properties (port (child) node):
- - #phy-cells : must be 0. See ./phy-bindings.txt for details.
- - interrupts : specify an interrupt for each entry in interrupt-names.
- - interrupt-names : a list which should be one of the following cases:
- Regular case:
- * "otg-id" : for the otg id interrupt.
- * "otg-bvalid" : for the otg vbus interrupt.
- * "linestate" : for the host/otg linestate interrupt.
- Some SoCs use one interrupt with the above muxed together, so for these
- * "otg-mux" : otg-port interrupt, which mux otg-id/otg-bvalid/linestate
- to one.
-
-Optional properties:
- - phy-supply : phandle to a regulator that provides power to VBUS.
- See ./phy-bindings.txt for details.
-
-Example:
-
-grf: syscon@ff770000 {
- compatible = "rockchip,rk3366-grf", "syscon", "simple-mfd";
- #address-cells = <1>;
- #size-cells = <1>;
-
-...
-
- u2phy: usb2-phy@700 {
- compatible = "rockchip,rk3366-usb2phy";
- reg = <0x700 0x2c>;
- #clock-cells = <0>;
- clock-output-names = "sclk_otgphy0_480m";
-
- u2phy_otg: otg-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "otg-id", "otg-bvalid", "linestate";
- };
-
- u2phy_host: host-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "linestate";
- };
- };
-};
diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
new file mode 100644
index 000000000000..cb71561a21b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
@@ -0,0 +1,155 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip USB2.0 phy with inno IP block
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+ compatible:
+ enum:
+ - rockchip,px30-usb2phy
+ - rockchip,rk3228-usb2phy
+ - rockchip,rk3328-usb2phy
+ - rockchip,rk3366-usb2phy
+ - rockchip,rk3399-usb2phy
+ - rockchip,rv1108-usb2phy
+
+ reg:
+ maxItems: 1
+
+ clock-output-names:
+ description:
+ The usb 480m output clock name.
+
+ "#clock-cells":
+ const: 0
+
+ "#phy-cells":
+ const: 0
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: phyclk
+
+ assigned-clocks:
+ description:
+ Phandle of the usb 480m clock.
+
+ assigned-clock-parents:
+ description:
+ Parent of the usb 480m clock.
+ Select between usb-phy output 480m and xin24m.
+ Refer to clk/clock-bindings.txt for generic clock consumer properties.
+
+ extcon:
+ description:
+ Phandle to the extcon device providing the cable state for the otg phy.
+
+ rockchip,usbgrf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the 'usb general register files'.
+ When set the driver will request its phandle as one companion-grf
+ for some special SoCs (e.g rv1108).
+
+ host-port:
+ type: object
+ additionalProperties: false
+
+ properties:
+ "#phy-cells":
+ const: 0
+
+ interrupts:
+ description: host linestate interrupt
+
+ interrupt-names:
+ const: linestate
+
+ phy-supply:
+ description:
+ Phandle to a regulator that provides power to VBUS.
+ See ./phy-bindings.txt for details.
+
+ required:
+ - "#phy-cells"
+ - interrupts
+ - interrupt-names
+
+ otg-port:
+ type: object
+ additionalProperties: false
+
+ properties:
+ "#phy-cells":
+ const: 0
+
+ interrupts:
+ minItems: 1
+ maxItems: 3
+
+ interrupt-names:
+ oneOf:
+ - const: linestate
+ - const: otg-mux
+ - items:
+ - const: otg-bvalid
+ - const: otg-id
+ - const: linestate
+
+ phy-supply:
+ description:
+ Phandle to a regulator that provides power to VBUS.
+ See ./phy-bindings.txt for details.
+
+ required:
+ - "#phy-cells"
+ - interrupts
+ - interrupt-names
+
+required:
+ - compatible
+ - reg
+ - clock-output-names
+ - "#clock-cells"
+ - "#phy-cells"
+ - host-port
+ - otg-port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3399-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ u2phy0: usb2-phy@e450 {
+ compatible = "rockchip,rk3399-usb2phy";
+ reg = <0xe450 0x10>;
+ clocks = <&cru SCLK_USB2PHY0_REF>;
+ clock-names = "phyclk";
+ clock-output-names = "clk_usbphy0_480m";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+
+ u2phy0_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "linestate";
+ };
+
+ u2phy0_otg: otg-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "otg-bvalid", "otg-id", "linestate";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
index 452cee1aed32..fd1982c56104 100644
--- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
+++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
@@ -159,6 +159,8 @@ required:
- "#reset-cells"
- ranges
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/soc/ti,sci_pm_domain.h>
diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml
index 135c7dfbc180..7651a675ab2d 100644
--- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml
@@ -57,6 +57,8 @@ patternProperties:
required:
- compatible
+additionalProperties: false
+
examples:
- |
syscon: scu@1e6e2000 {
diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml
index 824f7fd1d51b..36feaf5e2dff 100644
--- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml
@@ -70,6 +70,8 @@ required:
- compatible
- aspeed,external-nodes
+additionalProperties: false
+
examples:
- |
apb {
diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
index ac8d1c30a8ed..45af29bc3202 100644
--- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
@@ -92,6 +92,8 @@ patternProperties:
required:
- compatible
+additionalProperties: false
+
examples:
- |
syscon: scu@1e6e2000 {
diff --git a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt
deleted file mode 100644
index 8173b12138ad..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-UniPhier SoCs pin controller
-
-Required properties:
-- compatible: should be one of the following:
- "socionext,uniphier-ld4-pinctrl" - for LD4 SoC
- "socionext,uniphier-pro4-pinctrl" - for Pro4 SoC
- "socionext,uniphier-sld8-pinctrl" - for sLD8 SoC
- "socionext,uniphier-pro5-pinctrl" - for Pro5 SoC
- "socionext,uniphier-pxs2-pinctrl" - for PXs2 SoC
- "socionext,uniphier-ld6b-pinctrl" - for LD6b SoC
- "socionext,uniphier-ld11-pinctrl" - for LD11 SoC
- "socionext,uniphier-ld20-pinctrl" - for LD20 SoC
- "socionext,uniphier-pxs3-pinctrl" - for PXs3 SoC
-
-Note:
-The UniPhier pinctrl should be a subnode of a "syscon" compatible node.
-
-Example:
- soc-glue@5f800000 {
- compatible = "socionext,uniphier-pro4-soc-glue",
- "simple-mfd", "syscon";
- reg = <0x5f800000 0x2000>;
-
- pinctrl: pinctrl {
- compatible = "socionext,uniphier-pro4-pinctrl";
- };
- };
diff --git a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml
new file mode 100644
index 000000000000..f8a93d8680f9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/socionext,uniphier-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UniPhier SoCs pin controller
+
+maintainers:
+ - Masahiro Yamada <yamada.masahiro@socionext.com>
+
+properties:
+ $nodename:
+ pattern: "pinctrl"
+
+ compatible:
+ enum:
+ - socionext,uniphier-ld4-pinctrl
+ - socionext,uniphier-pro4-pinctrl
+ - socionext,uniphier-sld8-pinctrl
+ - socionext,uniphier-pro5-pinctrl
+ - socionext,uniphier-pxs2-pinctrl
+ - socionext,uniphier-ld6b-pinctrl
+ - socionext,uniphier-ld11-pinctrl
+ - socionext,uniphier-ld20-pinctrl
+ - socionext,uniphier-pxs3-pinctrl
+
+required:
+ - compatible
+
+examples:
+ - |
+ // The UniPhier pinctrl should be a subnode of a "syscon" compatible node.
+
+ soc-glue@5f800000 {
+ compatible = "socionext,uniphier-pro4-soc-glue", "simple-mfd", "syscon";
+ reg = <0x5f800000 0x2000>;
+
+ pinctrl: pinctrl {
+ compatible = "socionext,uniphier-pro4-pinctrl";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
index ef4de32cb17c..46a0478cb924 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
@@ -194,6 +194,8 @@ required:
- ranges
- pins-are-numbered
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml b/Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml
index d3098c924b25..6c6079fe1351 100644
--- a/Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml
+++ b/Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml
@@ -68,6 +68,8 @@ required:
- "#power-domain-cells"
- amlogic,ao-sysctrl
+additionalProperties: false
+
examples:
- |
pwrc: power-controller {
diff --git a/Documentation/devicetree/bindings/power/power-domain.yaml b/Documentation/devicetree/bindings/power/power-domain.yaml
index 6047aacd7766..ff5936e4a215 100644
--- a/Documentation/devicetree/bindings/power/power-domain.yaml
+++ b/Documentation/devicetree/bindings/power/power-domain.yaml
@@ -114,18 +114,18 @@ examples:
domain-idle-states = <&DOMAIN_PWR_DN>;
};
- DOMAIN_RET: state@0 {
- compatible = "domain-idle-state";
- reg = <0x0 0x0>;
- entry-latency-us = <1000>;
- exit-latency-us = <2000>;
- min-residency-us = <10000>;
- };
-
- DOMAIN_PWR_DN: state@1 {
- compatible = "domain-idle-state";
- reg = <0x1 0x0>;
- entry-latency-us = <5000>;
- exit-latency-us = <8000>;
- min-residency-us = <7000>;
+ domain-idle-states {
+ DOMAIN_RET: domain-retention {
+ compatible = "domain-idle-state";
+ entry-latency-us = <1000>;
+ exit-latency-us = <2000>;
+ min-residency-us = <10000>;
+ };
+
+ DOMAIN_PWR_DN: domain-pwr-dn {
+ compatible = "domain-idle-state";
+ entry-latency-us = <5000>;
+ exit-latency-us = <8000>;
+ min-residency-us = <7000>;
+ };
};
diff --git a/Documentation/devicetree/bindings/power/renesas,apmu.txt b/Documentation/devicetree/bindings/power/renesas,apmu.txt
deleted file mode 100644
index 5f24586c8cf3..000000000000
--- a/Documentation/devicetree/bindings/power/renesas,apmu.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-DT bindings for the Renesas Advanced Power Management Unit
-
-Renesas R-Car and RZ/G1 SoCs utilize one or more APMU hardware units
-for CPU core power domain control including SMP boot and CPU Hotplug.
-
-Required properties:
-
-- compatible: Should be "renesas,<soctype>-apmu", "renesas,apmu" as fallback.
- Examples with soctypes are:
- - "renesas,r8a7743-apmu" (RZ/G1M)
- - "renesas,r8a7744-apmu" (RZ/G1N)
- - "renesas,r8a7745-apmu" (RZ/G1E)
- - "renesas,r8a77470-apmu" (RZ/G1C)
- - "renesas,r8a7790-apmu" (R-Car H2)
- - "renesas,r8a7791-apmu" (R-Car M2-W)
- - "renesas,r8a7792-apmu" (R-Car V2H)
- - "renesas,r8a7793-apmu" (R-Car M2-N)
- - "renesas,r8a7794-apmu" (R-Car E2)
-
-- reg: Base address and length of the I/O registers used by the APMU.
-
-- cpus: This node contains a list of CPU cores, which should match the order
- of CPU cores used by the WUPCR and PSTR registers in the Advanced Power
- Management Unit section of the device's datasheet.
-
-
-Example:
-
-This shows the r8a7791 APMU that can control CPU0 and CPU1.
-
- apmu@e6152000 {
- compatible = "renesas,r8a7791-apmu", "renesas,apmu";
- reg = <0 0xe6152000 0 0x188>;
- cpus = <&cpu0 &cpu1>;
- };
diff --git a/Documentation/devicetree/bindings/power/renesas,apmu.yaml b/Documentation/devicetree/bindings/power/renesas,apmu.yaml
new file mode 100644
index 000000000000..078b2cb40fe3
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/renesas,apmu.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/power/renesas,apmu.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Renesas Advanced Power Management Unit
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+ - Magnus Damm <magnus.damm@gmail.com>
+
+description:
+ Renesas R-Car Gen2 and RZ/G1 SoCs utilize one or more APMU hardware units for
+ CPU core power domain control including SMP boot and CPU Hotplug.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r8a7743-apmu # RZ/G1M
+ - renesas,r8a7744-apmu # RZ/G1N
+ - renesas,r8a7745-apmu # RZ/G1E
+ - renesas,r8a77470-apmu # RZ/G1C
+ - renesas,r8a7790-apmu # R-Car H2
+ - renesas,r8a7791-apmu # R-Car M2-W
+ - renesas,r8a7792-apmu # R-Car V2H
+ - renesas,r8a7793-apmu # R-Car M2-N
+ - renesas,r8a7794-apmu # R-Car E2
+ - const: renesas,apmu
+
+ reg:
+ maxItems: 1
+
+ cpus:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ Array of phandles pointing to CPU cores, which should match the order of
+ CPU cores used by the WUPCR and PSTR registers in the Advanced Power
+ Management Unit section of the device's datasheet.
+
+required:
+ - compatible
+ - reg
+ - cpus
+
+additionalProperties: false
+
+examples:
+ - |
+ apmu@e6152000 {
+ compatible = "renesas,r8a7791-apmu", "renesas,apmu";
+ reg = <0xe6152000 0x188>;
+ cpus = <&cpu0 &cpu1>;
+ };
diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
deleted file mode 100644
index acb41fade926..000000000000
--- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
+++ /dev/null
@@ -1,62 +0,0 @@
-DT bindings for the Renesas R-Car (RZ/G) System Controller
-
-== System Controller Node ==
-
-The R-Car (RZ/G) System Controller provides power management for the CPU cores
-and various coprocessors.
-
-Required properties:
- - compatible: Must contain exactly one of the following:
- - "renesas,r8a7743-sysc" (RZ/G1M)
- - "renesas,r8a7744-sysc" (RZ/G1N)
- - "renesas,r8a7745-sysc" (RZ/G1E)
- - "renesas,r8a77470-sysc" (RZ/G1C)
- - "renesas,r8a774a1-sysc" (RZ/G2M)
- - "renesas,r8a774b1-sysc" (RZ/G2N)
- - "renesas,r8a774c0-sysc" (RZ/G2E)
- - "renesas,r8a7779-sysc" (R-Car H1)
- - "renesas,r8a7790-sysc" (R-Car H2)
- - "renesas,r8a7791-sysc" (R-Car M2-W)
- - "renesas,r8a7792-sysc" (R-Car V2H)
- - "renesas,r8a7793-sysc" (R-Car M2-N)
- - "renesas,r8a7794-sysc" (R-Car E2)
- - "renesas,r8a7795-sysc" (R-Car H3)
- - "renesas,r8a7796-sysc" (R-Car M3-W)
- - "renesas,r8a77961-sysc" (R-Car M3-W+)
- - "renesas,r8a77965-sysc" (R-Car M3-N)
- - "renesas,r8a77970-sysc" (R-Car V3M)
- - "renesas,r8a77980-sysc" (R-Car V3H)
- - "renesas,r8a77990-sysc" (R-Car E3)
- - "renesas,r8a77995-sysc" (R-Car D3)
- - reg: Address start and address range for the device.
- - #power-domain-cells: Must be 1.
-
-
-Example:
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,r8a7791-sysc";
- reg = <0 0xe6180000 0 0x0200>;
- #power-domain-cells = <1>;
- };
-
-
-== PM Domain Consumers ==
-
-Devices residing in a power area must refer to that power area, as documented
-by the generic PM domain bindings in
-Documentation/devicetree/bindings/power/power_domain.txt.
-
-Required properties:
- - power-domains: A phandle and symbolic PM domain specifier, as defined in
- <dt-bindings/power/r8a77*-sysc.h>.
-
-
-Example:
-
- L2_CA15: cache-controller@0 {
- compatible = "cache";
- power-domains = <&sysc R8A7791_PD_CA15_SCU>;
- cache-unified;
- cache-level = <2>;
- };
diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml
new file mode 100644
index 000000000000..e59331e1d944
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/power/renesas,rcar-sysc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Renesas R-Car and RZ/G System Controller
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+ - Magnus Damm <magnus.damm@gmail.com>
+
+description:
+ The R-Car (RZ/G) System Controller provides power management for the CPU
+ cores and various coprocessors.
+
+properties:
+ compatible:
+ enum:
+ - renesas,r8a7743-sysc # RZ/G1M
+ - renesas,r8a7744-sysc # RZ/G1N
+ - renesas,r8a7745-sysc # RZ/G1E
+ - renesas,r8a77470-sysc # RZ/G1C
+ - renesas,r8a774a1-sysc # RZ/G2M
+ - renesas,r8a774b1-sysc # RZ/G2N
+ - renesas,r8a774c0-sysc # RZ/G2E
+ - renesas,r8a7779-sysc # R-Car H1
+ - renesas,r8a7790-sysc # R-Car H2
+ - renesas,r8a7791-sysc # R-Car M2-W
+ - renesas,r8a7792-sysc # R-Car V2H
+ - renesas,r8a7793-sysc # R-Car M2-N
+ - renesas,r8a7794-sysc # R-Car E2
+ - renesas,r8a7795-sysc # R-Car H3
+ - renesas,r8a77961-sysc # R-Car M3-W+
+ - renesas,r8a77965-sysc # R-Car M3-N
+ - renesas,r8a7796-sysc # R-Car M3-W
+ - renesas,r8a77970-sysc # R-Car V3M
+ - renesas,r8a77980-sysc # R-Car V3H
+ - renesas,r8a77990-sysc # R-Car E3
+ - renesas,r8a77995-sysc # R-Car D3
+
+ reg:
+ maxItems: 1
+
+ '#power-domain-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ // System Controller node
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a7791-sysc";
+ reg = <0xe6180000 0x0200>;
+ #power-domain-cells = <1>;
+ };
+
+ - |
+ // Power Domain consumers
+ #include <dt-bindings/power/r8a7791-sysc.h>
+
+ cache-controller-0 {
+ compatible = "cache";
+ power-domains = <&sysc R8A7791_PD_CA15_SCU>;
+ cache-unified;
+ cache-level = <2>;
+ };
diff --git a/Documentation/devicetree/bindings/power/reset/syscon-poweroff.yaml b/Documentation/devicetree/bindings/power/reset/syscon-poweroff.yaml
index 520e07e6f21b..3412fe7e1e80 100644
--- a/Documentation/devicetree/bindings/power/reset/syscon-poweroff.yaml
+++ b/Documentation/devicetree/bindings/power/reset/syscon-poweroff.yaml
@@ -41,6 +41,8 @@ required:
- regmap
- offset
+additionalProperties: false
+
allOf:
- if:
not:
diff --git a/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml b/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml
index d38006b1f1f4..b80772cb9f06 100644
--- a/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml
+++ b/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml
@@ -41,6 +41,8 @@ required:
- regmap
- offset
+additionalProperties: false
+
allOf:
- if:
not:
diff --git a/Documentation/devicetree/bindings/power/supply/max77650-charger.yaml b/Documentation/devicetree/bindings/power/supply/max77650-charger.yaml
index deef010ec535..62eeddb65aed 100644
--- a/Documentation/devicetree/bindings/power/supply/max77650-charger.yaml
+++ b/Documentation/devicetree/bindings/power/supply/max77650-charger.yaml
@@ -32,3 +32,6 @@ properties:
required:
- compatible
+additionalProperties: false
+
+...
diff --git a/Documentation/devicetree/bindings/ptp/ptp-idtcm.yaml b/Documentation/devicetree/bindings/ptp/ptp-idtcm.yaml
index 9e21b83d717e..239b49fad805 100644
--- a/Documentation/devicetree/bindings/ptp/ptp-idtcm.yaml
+++ b/Documentation/devicetree/bindings/ptp/ptp-idtcm.yaml
@@ -55,6 +55,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
i2c@1 {
diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt
index 95536d83c5f2..29adff59c479 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt
@@ -19,10 +19,15 @@ Required properties:
- "pwm1-8": the eight per PWM clocks for mt2712
- "pwm1-6": the six per PWM clocks for mt7622
- "pwm1-5": the five per PWM clocks for mt7623
+ - "pwm1" : the PWM1 clock for mt7629
- pinctrl-names: Must contain a "default" entry.
- pinctrl-0: One property must exist for each entry in pinctrl-names.
See pinctrl/pinctrl-bindings.txt for details of the property values.
+Optional properties:
+- assigned-clocks: Reference to the PWM clock entries.
+- assigned-clock-parents: The phandle of the parent clock of PWM clock.
+
Example:
pwm0: pwm@11006000 {
compatible = "mediatek,mt7623-pwm";
diff --git a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml
index 4969a954993c..4bf62a3d5bba 100644
--- a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml
@@ -19,6 +19,10 @@ properties:
- renesas,tpu-r8a7744 # RZ/G1N
- renesas,tpu-r8a7745 # RZ/G1E
- renesas,tpu-r8a7790 # R-Car H2
+ - renesas,tpu-r8a7791 # R-Car M2-W
+ - renesas,tpu-r8a7792 # R-Car V2H
+ - renesas,tpu-r8a7793 # R-Car M2-N
+ - renesas,tpu-r8a7794 # R-Car E2
- renesas,tpu-r8a7795 # R-Car H3
- renesas,tpu-r8a7796 # R-Car M3-W
- renesas,tpu-r8a77965 # R-Car M3-N
diff --git a/Documentation/devicetree/bindings/regulator/max77650-regulator.yaml b/Documentation/devicetree/bindings/regulator/max77650-regulator.yaml
index 7d724159f890..ce0a4021ae7f 100644
--- a/Documentation/devicetree/bindings/regulator/max77650-regulator.yaml
+++ b/Documentation/devicetree/bindings/regulator/max77650-regulator.yaml
@@ -24,8 +24,11 @@ properties:
const: maxim,max77650-regulator
patternProperties:
- "^regulator@[0-3]$":
+ "^regulator-(ldo|sbb[0-2])$":
$ref: "regulator.yaml#"
required:
- compatible
+additionalProperties: false
+
+...
diff --git a/Documentation/devicetree/bindings/regulator/st,stpmic1-regulator.txt b/Documentation/devicetree/bindings/regulator/st,stpmic1-regulator.txt
deleted file mode 100644
index 6189df71ea98..000000000000
--- a/Documentation/devicetree/bindings/regulator/st,stpmic1-regulator.txt
+++ /dev/null
@@ -1,64 +0,0 @@
-STMicroelectronics STPMIC1 Voltage regulators
-
-Regulator Nodes are optional depending on needs.
-
-Available Regulators in STPMIC1 device are:
- - buck1 for Buck BUCK1
- - buck2 for Buck BUCK2
- - buck3 for Buck BUCK3
- - buck4 for Buck BUCK4
- - ldo1 for LDO LDO1
- - ldo2 for LDO LDO2
- - ldo3 for LDO LDO3
- - ldo4 for LDO LDO4
- - ldo5 for LDO LDO5
- - ldo6 for LDO LDO6
- - vref_ddr for LDO Vref DDR
- - boost for Buck BOOST
- - pwr_sw1 for VBUS_OTG switch
- - pwr_sw2 for SW_OUT switch
-
-Switches are fixed voltage regulators with only enable/disable capability.
-
-Optional properties:
-- st,mask-reset: mask reset for this regulator: the regulator configuration
- is maintained during pmic reset.
-- regulator-over-current-protection:
- if set, all regulators are switched off in case of over-current detection
- on this regulator,
- if not set, the driver only sends an over-current event.
-- interrupts: index of current limit detection interrupt
-- <regulator>-supply: phandle to the parent supply/regulator node
- each regulator supply can be described except vref_ddr.
-- regulator-active-discharge: can be used on pwr_sw1 and pwr_sw2.
-
-Example:
-regulators {
- compatible = "st,stpmic1-regulators";
-
- ldo6-supply = <&v3v3>;
-
- vdd_core: buck1 {
- regulator-name = "vdd_core";
- interrupts = <IT_CURLIM_BUCK1 0>;
- st,mask-reset;
- regulator-pull-down;
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1200000>;
- };
-
- v3v3: buck4 {
- regulator-name = "v3v3";
- interrupts = <IT_CURLIM_BUCK4 0>;
-
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- v1v8: ldo6 {
- regulator-name = "v1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-over-current-protection;
- };
-};
diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml
index b3f57d81f007..92922d3afd14 100644
--- a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml
+++ b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml
@@ -29,6 +29,8 @@ required:
- reg
- "#reset-cells"
+additionalProperties: false
+
examples:
- |
reset-controller@c884404 {
diff --git a/Documentation/devicetree/bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml b/Documentation/devicetree/bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml
index 411bd76f1b64..512a33bdb208 100644
--- a/Documentation/devicetree/bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml
+++ b/Documentation/devicetree/bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml
@@ -28,6 +28,8 @@ required:
- reg
- "#reset-cells"
+additionalProperties: false
+
examples:
- |
reset-controller@8b2c800 {
diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.txt b/Documentation/devicetree/bindings/reset/renesas,rst.txt
deleted file mode 100644
index de7f06ccd003..000000000000
--- a/Documentation/devicetree/bindings/reset/renesas,rst.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-DT bindings for the Renesas R-Car and RZ/G Reset Controllers
-
-The R-Car and RZ/G Reset Controllers provide reset control, and implement the
-following functions:
- - Latching of the levels on mode pins when PRESET# is negated,
- - Mode monitoring register,
- - Reset control of peripheral devices (on R-Car Gen1),
- - Watchdog timer (on R-Car Gen1),
- - Register-based reset control and boot address registers for the various CPU
- cores (on R-Car Gen2 and Gen3, and on RZ/G).
-
-
-Required properties:
- - compatible: Should be
- - "renesas,<soctype>-reset-wdt" for R-Car Gen1,
- - "renesas,<soctype>-rst" for R-Car Gen2 and Gen3, and RZ/G
- Examples with soctypes are:
- - "renesas,r8a7743-rst" (RZ/G1M)
- - "renesas,r8a7744-rst" (RZ/G1N)
- - "renesas,r8a7745-rst" (RZ/G1E)
- - "renesas,r8a77470-rst" (RZ/G1C)
- - "renesas,r8a774a1-rst" (RZ/G2M)
- - "renesas,r8a774b1-rst" (RZ/G2N)
- - "renesas,r8a774c0-rst" (RZ/G2E)
- - "renesas,r8a7778-reset-wdt" (R-Car M1A)
- - "renesas,r8a7779-reset-wdt" (R-Car H1)
- - "renesas,r8a7790-rst" (R-Car H2)
- - "renesas,r8a7791-rst" (R-Car M2-W)
- - "renesas,r8a7792-rst" (R-Car V2H
- - "renesas,r8a7793-rst" (R-Car M2-N)
- - "renesas,r8a7794-rst" (R-Car E2)
- - "renesas,r8a7795-rst" (R-Car H3)
- - "renesas,r8a7796-rst" (R-Car M3-W)
- - "renesas,r8a77961-rst" (R-Car M3-W+)
- - "renesas,r8a77965-rst" (R-Car M3-N)
- - "renesas,r8a77970-rst" (R-Car V3M)
- - "renesas,r8a77980-rst" (R-Car V3H)
- - "renesas,r8a77990-rst" (R-Car E3)
- - "renesas,r8a77995-rst" (R-Car D3)
- - reg: Address start and address range for the device.
-
-
-Example:
-
- rst: reset-controller@e6160000 {
- compatible = "renesas,r8a7795-rst";
- reg = <0 0xe6160000 0 0x0200>;
- };
diff --git a/Documentation/devicetree/bindings/reset/renesas,rst.yaml b/Documentation/devicetree/bindings/reset/renesas,rst.yaml
new file mode 100644
index 000000000000..b5de1d196a13
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/renesas,rst.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/reset/renesas,rst.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Renesas R-Car and RZ/G Reset Controller
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+ - Magnus Damm <magnus.damm@gmail.com>
+
+description: |
+ The R-Car and RZ/G Reset Controllers provide reset control, and implement the
+ following functions:
+ - Latching of the levels on mode pins when PRESET# is negated,
+ - Mode monitoring register,
+ - Reset control of peripheral devices (on R-Car Gen1),
+ - Watchdog timer (on R-Car Gen1),
+ - Register-based reset control and boot address registers for the various
+ CPU cores (on R-Car Gen2 and Gen3, and on RZ/G).
+
+properties:
+ compatible:
+ enum:
+ - renesas,r8a7743-rst # RZ/G1M
+ - renesas,r8a7744-rst # RZ/G1N
+ - renesas,r8a7745-rst # RZ/G1E
+ - renesas,r8a77470-rst # RZ/G1C
+ - renesas,r8a774a1-rst # RZ/G2M
+ - renesas,r8a774b1-rst # RZ/G2N
+ - renesas,r8a774c0-rst # RZ/G2E
+ - renesas,r8a7778-reset-wdt # R-Car M1A
+ - renesas,r8a7779-reset-wdt # R-Car H1
+ - renesas,r8a7790-rst # R-Car H2
+ - renesas,r8a7791-rst # R-Car M2-W
+ - renesas,r8a7792-rst # R-Car V2H
+ - renesas,r8a7793-rst # R-Car M2-N
+ - renesas,r8a7794-rst # R-Car E2
+ - renesas,r8a7795-rst # R-Car H3
+ - renesas,r8a7796-rst # R-Car M3-W
+ - renesas,r8a77961-rst # R-Car M3-W+
+ - renesas,r8a77965-rst # R-Car M3-N
+ - renesas,r8a77970-rst # R-Car V3M
+ - renesas,r8a77980-rst # R-Car V3H
+ - renesas,r8a77990-rst # R-Car E3
+ - renesas,r8a77995-rst # R-Car D3
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a7795-rst";
+ reg = <0xe6160000 0x0200>;
+ };
diff --git a/Documentation/devicetree/bindings/rng/amlogic,meson-rng.yaml b/Documentation/devicetree/bindings/rng/amlogic,meson-rng.yaml
index a9ff3cb35c5e..444be32a8a29 100644
--- a/Documentation/devicetree/bindings/rng/amlogic,meson-rng.yaml
+++ b/Documentation/devicetree/bindings/rng/amlogic,meson-rng.yaml
@@ -29,6 +29,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
rng@c8834000 {
diff --git a/Documentation/devicetree/bindings/rng/brcm,bcm2835.txt b/Documentation/devicetree/bindings/rng/brcm,bcm2835.txt
deleted file mode 100644
index aaac7975f61c..000000000000
--- a/Documentation/devicetree/bindings/rng/brcm,bcm2835.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-BCM2835/6368 Random number generator
-
-Required properties:
-
-- compatible : should be one of
- "brcm,bcm2835-rng"
- "brcm,bcm-nsp-rng"
- "brcm,bcm5301x-rng" or
- "brcm,bcm6368-rng"
-- reg : Specifies base physical address and size of the registers.
-
-Optional properties:
-
-- clocks : phandle to clock-controller plus clock-specifier pair
-- clock-names : "ipsec" as a clock name
-
-Optional properties:
-
-- interrupts: specify the interrupt for the RNG block
-
-Example:
-
-rng {
- compatible = "brcm,bcm2835-rng";
- reg = <0x7e104000 0x10>;
- interrupts = <2 29>;
-};
-
-rng@18033000 {
- compatible = "brcm,bcm-nsp-rng";
- reg = <0x18033000 0x14>;
-};
-
-random: rng@10004180 {
- compatible = "brcm,bcm6368-rng";
- reg = <0x10004180 0x14>;
-
- clocks = <&periph_clk 18>;
- clock-names = "ipsec";
-};
diff --git a/Documentation/devicetree/bindings/rng/brcm,bcm2835.yaml b/Documentation/devicetree/bindings/rng/brcm,bcm2835.yaml
new file mode 100644
index 000000000000..89ab67f20a7f
--- /dev/null
+++ b/Documentation/devicetree/bindings/rng/brcm,bcm2835.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rng/brcm,bcm2835.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: BCM2835/6368 Random number generator
+
+maintainers:
+ - Stefan Wahren <stefan.wahren@i2se.com>
+ - Florian Fainelli <f.fainelli@gmail.com>
+ - Herbert Xu <herbert@gondor.apana.org.au>
+
+properties:
+ compatible:
+ enum:
+ - brcm,bcm2835-rng
+ - brcm,bcm-nsp-rng
+ - brcm,bcm5301x-rng
+ - brcm,bcm6368-rng
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: ipsec
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ rng {
+ compatible = "brcm,bcm2835-rng";
+ reg = <0x7e104000 0x10>;
+ interrupts = <2 29>;
+ };
+
+ - |
+ rng@18033000 {
+ compatible = "brcm,bcm-nsp-rng";
+ reg = <0x18033000 0x14>;
+ };
+
+ - |
+ rng@10004180 {
+ compatible = "brcm,bcm6368-rng";
+ reg = <0x10004180 0x14>;
+
+ clocks = <&periph_clk 18>;
+ clock-names = "ipsec";
+ };
diff --git a/Documentation/devicetree/bindings/rtc/renesas,sh-rtc.yaml b/Documentation/devicetree/bindings/rtc/renesas,sh-rtc.yaml
index dcff573cbdb1..b95cb017f469 100644
--- a/Documentation/devicetree/bindings/rtc/renesas,sh-rtc.yaml
+++ b/Documentation/devicetree/bindings/rtc/renesas,sh-rtc.yaml
@@ -51,6 +51,8 @@ required:
- clocks
- clock-names
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/r7s72100-clock.h>
diff --git a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml
index 0a54296d7218..48c6cafca90c 100644
--- a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml
+++ b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml
@@ -111,6 +111,8 @@ required:
- clocks
- interrupts
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/mfd/stm32f4-rcc.h>
diff --git a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml
index 214fe8beddc3..d4178ab0d675 100644
--- a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml
@@ -62,6 +62,8 @@ required:
- clocks
- clock-names
+additionalProperties: false
+
examples:
- |
serial@84c0 {
diff --git a/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt b/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt
index c8d677f9491f..9582fc2279ed 100644
--- a/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt
+++ b/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt
@@ -19,7 +19,7 @@ Optional properties:
the transceiver is actually CTS_B, not RTS_B. CTS_B is always output,
and RTS_B is input, regardless of dte-mode.
-Please check Documentation/devicetree/bindings/serial/serial.txt
+Please check Documentation/devicetree/bindings/serial/serial.yaml
for the complete list of generic properties.
Note: Each uart controller should have an alias correctly numbered
diff --git a/Documentation/devicetree/bindings/serial/renesas,hscif.yaml b/Documentation/devicetree/bindings/serial/renesas,hscif.yaml
new file mode 100644
index 000000000000..91101521ef07
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/renesas,hscif.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/serial/renesas,hscif.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Renesas High Speed Serial Communication Interface with FIFO (HSCIF)
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+allOf:
+ - $ref: serial.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - renesas,hscif-r8a7778 # R-Car M1
+ - renesas,hscif-r8a7779 # R-Car H1
+ - const: renesas,rcar-gen1-hscif # R-Car Gen1
+ - const: renesas,hscif # generic HSCIF compatible UART
+
+ - items:
+ - enum:
+ - renesas,hscif-r8a7743 # RZ/G1M
+ - renesas,hscif-r8a7744 # RZ/G1N
+ - renesas,hscif-r8a7745 # RZ/G1E
+ - renesas,hscif-r8a77470 # RZ/G1C
+ - renesas,hscif-r8a7790 # R-Car H2
+ - renesas,hscif-r8a7791 # R-Car M2-W
+ - renesas,hscif-r8a7792 # R-Car V2H
+ - renesas,hscif-r8a7793 # R-Car M2-N
+ - renesas,hscif-r8a7794 # R-Car E2
+ - const: renesas,rcar-gen2-hscif # R-Car Gen2 and RZ/G1
+ - const: renesas,hscif # generic HSCIF compatible UART
+
+ - items:
+ - enum:
+ - renesas,hscif-r8a774a1 # RZ/G2M
+ - renesas,hscif-r8a774b1 # RZ/G2N
+ - renesas,hscif-r8a774c0 # RZ/G2E
+ - renesas,hscif-r8a7795 # R-Car H3
+ - renesas,hscif-r8a7796 # R-Car M3-W
+ - renesas,hscif-r8a77961 # R-Car M3-W+
+ - renesas,hscif-r8a77965 # R-Car M3-N
+ - renesas,hscif-r8a77970 # R-Car V3M
+ - renesas,hscif-r8a77980 # R-Car V3H
+ - renesas,hscif-r8a77990 # R-Car E3
+ - renesas,hscif-r8a77995 # R-Car D3
+ - const: renesas,rcar-gen3-hscif # R-Car Gen3 and RZ/G2
+ - const: renesas,hscif # generic HSCIF compatible UART
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 4
+
+ clock-names:
+ minItems: 1
+ maxItems: 4
+ items:
+ enum:
+ - fck # UART functional clock
+ - hsck # optional external clock input
+ - brg_int # optional internal clock source for BRG frequency divider
+ - scif_clk # optional external clock source for BRG frequency divider
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ dmas:
+ description:
+ Must contain a list of pairs of references to DMA specifiers, one for
+ transmission, and one for reception.
+
+ dma-names:
+ minItems: 2
+ maxItems: 4
+ items:
+ enum:
+ - tx
+ - rx
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,rcar-gen2-hscif
+ - renesas,rcar-gen3-hscif
+then:
+ required:
+ - resets
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7795-sysc.h>
+ aliases {
+ serial1 = &hscif1;
+ };
+
+ hscif1: serial@e6550000 {
+ compatible = "renesas,hscif-r8a7795", "renesas,rcar-gen3-hscif",
+ "renesas,hscif";
+ reg = <0xe6550000 96>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 519>, <&cpg CPG_CORE R8A7795_CLK_S3D1>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac1 0x33>, <&dmac1 0x32>, <&dmac2 0x33>, <&dmac2 0x32>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 519>;
+ uart-has-rtscts;
+ };
diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
deleted file mode 100644
index a5edf4b70c7a..000000000000
--- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+++ /dev/null
@@ -1,150 +0,0 @@
-* Renesas SH-Mobile Serial Communication Interface
-
-Required properties:
-
- - compatible: Must contain one or more of the following:
-
- - "renesas,scif-r7s72100" for R7S72100 (RZ/A1H) SCIF compatible UART.
- - "renesas,scif-r7s9210" for R7S9210 (RZ/A2) SCIF compatible UART.
- - "renesas,scifa-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFA compatible UART.
- - "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART.
- - "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART.
- - "renesas,scifb-r8a7740" for R8A7740 (R-Mobile A1) SCIFB compatible UART.
- - "renesas,scif-r8a7743" for R8A7743 (RZ/G1M) SCIF compatible UART.
- - "renesas,scifa-r8a7743" for R8A7743 (RZ/G1M) SCIFA compatible UART.
- - "renesas,scifb-r8a7743" for R8A7743 (RZ/G1M) SCIFB compatible UART.
- - "renesas,hscif-r8a7743" for R8A7743 (RZ/G1M) HSCIF compatible UART.
- - "renesas,scif-r8a7744" for R8A7744 (RZ/G1N) SCIF compatible UART.
- - "renesas,scifa-r8a7744" for R8A7744 (RZ/G1N) SCIFA compatible UART.
- - "renesas,scifb-r8a7744" for R8A7744 (RZ/G1N) SCIFB compatible UART.
- - "renesas,hscif-r8a7744" for R8A7744 (RZ/G1N) HSCIF compatible UART.
- - "renesas,scif-r8a7745" for R8A7745 (RZ/G1E) SCIF compatible UART.
- - "renesas,scifa-r8a7745" for R8A7745 (RZ/G1E) SCIFA compatible UART.
- - "renesas,scifb-r8a7745" for R8A7745 (RZ/G1E) SCIFB compatible UART.
- - "renesas,hscif-r8a7745" for R8A7745 (RZ/G1E) HSCIF compatible UART.
- - "renesas,scif-r8a77470" for R8A77470 (RZ/G1C) SCIF compatible UART.
- - "renesas,hscif-r8a77470" for R8A77470 (RZ/G1C) HSCIF compatible UART.
- - "renesas,scif-r8a774a1" for R8A774A1 (RZ/G2M) SCIF compatible UART.
- - "renesas,hscif-r8a774a1" for R8A774A1 (RZ/G2M) HSCIF compatible UART.
- - "renesas,scif-r8a774b1" for R8A774B1 (RZ/G2N) SCIF compatible UART.
- - "renesas,hscif-r8a774b1" for R8A774B1 (RZ/G2N) HSCIF compatible UART.
- - "renesas,scif-r8a774c0" for R8A774C0 (RZ/G2E) SCIF compatible UART.
- - "renesas,hscif-r8a774c0" for R8A774C0 (RZ/G2E) HSCIF compatible UART.
- - "renesas,scif-r8a7778" for R8A7778 (R-Car M1) SCIF compatible UART.
- - "renesas,hscif-r8a7778" for R8A7778 (R-Car M1) HSCIF compatible UART.
- - "renesas,scif-r8a7779" for R8A7779 (R-Car H1) SCIF compatible UART.
- - "renesas,hscif-r8a7779" for R8A7779 (R-Car H1) HSCIF compatible UART.
- - "renesas,scif-r8a7790" for R8A7790 (R-Car H2) SCIF compatible UART.
- - "renesas,scifa-r8a7790" for R8A7790 (R-Car H2) SCIFA compatible UART.
- - "renesas,scifb-r8a7790" for R8A7790 (R-Car H2) SCIFB compatible UART.
- - "renesas,hscif-r8a7790" for R8A7790 (R-Car H2) HSCIF compatible UART.
- - "renesas,scif-r8a7791" for R8A7791 (R-Car M2-W) SCIF compatible UART.
- - "renesas,scifa-r8a7791" for R8A7791 (R-Car M2-W) SCIFA compatible UART.
- - "renesas,scifb-r8a7791" for R8A7791 (R-Car M2-W) SCIFB compatible UART.
- - "renesas,hscif-r8a7791" for R8A7791 (R-Car M2-W) HSCIF compatible UART.
- - "renesas,scif-r8a7792" for R8A7792 (R-Car V2H) SCIF compatible UART.
- - "renesas,hscif-r8a7792" for R8A7792 (R-Car V2H) HSCIF compatible UART.
- - "renesas,scif-r8a7793" for R8A7793 (R-Car M2-N) SCIF compatible UART.
- - "renesas,scifa-r8a7793" for R8A7793 (R-Car M2-N) SCIFA compatible UART.
- - "renesas,scifb-r8a7793" for R8A7793 (R-Car M2-N) SCIFB compatible UART.
- - "renesas,hscif-r8a7793" for R8A7793 (R-Car M2-N) HSCIF compatible UART.
- - "renesas,scif-r8a7794" for R8A7794 (R-Car E2) SCIF compatible UART.
- - "renesas,scifa-r8a7794" for R8A7794 (R-Car E2) SCIFA compatible UART.
- - "renesas,scifb-r8a7794" for R8A7794 (R-Car E2) SCIFB compatible UART.
- - "renesas,hscif-r8a7794" for R8A7794 (R-Car E2) HSCIF compatible UART.
- - "renesas,scif-r8a7795" for R8A7795 (R-Car H3) SCIF compatible UART.
- - "renesas,hscif-r8a7795" for R8A7795 (R-Car H3) HSCIF compatible UART.
- - "renesas,scif-r8a7796" for R8A77960 (R-Car M3-W) SCIF compatible UART.
- - "renesas,hscif-r8a7796" for R8A77960 (R-Car M3-W) HSCIF compatible UART.
- - "renesas,scif-r8a77961" for R8A77961 (R-Car M3-W+) SCIF compatible UART.
- - "renesas,hscif-r8a77961" for R8A77961 (R-Car M3-W+) HSCIF compatible UART.
- - "renesas,scif-r8a77965" for R8A77965 (R-Car M3-N) SCIF compatible UART.
- - "renesas,hscif-r8a77965" for R8A77965 (R-Car M3-N) HSCIF compatible UART.
- - "renesas,scif-r8a77970" for R8A77970 (R-Car V3M) SCIF compatible UART.
- - "renesas,hscif-r8a77970" for R8A77970 (R-Car V3M) HSCIF compatible UART.
- - "renesas,scif-r8a77980" for R8A77980 (R-Car V3H) SCIF compatible UART.
- - "renesas,hscif-r8a77980" for R8A77980 (R-Car V3H) HSCIF compatible UART.
- - "renesas,scif-r8a77990" for R8A77990 (R-Car E3) SCIF compatible UART.
- - "renesas,hscif-r8a77990" for R8A77990 (R-Car E3) HSCIF compatible UART.
- - "renesas,scif-r8a77995" for R8A77995 (R-Car D3) SCIF compatible UART.
- - "renesas,hscif-r8a77995" for R8A77995 (R-Car D3) HSCIF compatible UART.
- - "renesas,scifa-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFA compatible UART.
- - "renesas,scifb-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFB compatible UART.
- - "renesas,rcar-gen1-scif" for R-Car Gen1 SCIF compatible UART,
- - "renesas,rcar-gen2-scif" for R-Car Gen2 and RZ/G1 SCIF compatible UART,
- - "renesas,rcar-gen3-scif" for R-Car Gen3 and RZ/G2 SCIF compatible UART,
- - "renesas,rcar-gen2-scifa" for R-Car Gen2 and RZ/G1 SCIFA compatible UART,
- - "renesas,rcar-gen2-scifb" for R-Car Gen2 and RZ/G1 SCIFB compatible UART,
- - "renesas,rcar-gen1-hscif" for R-Car Gen1 HSCIF compatible UART,
- - "renesas,rcar-gen2-hscif" for R-Car Gen2 and RZ/G1 HSCIF compatible UART,
- - "renesas,rcar-gen3-hscif" for R-Car Gen3 and RZ/G2 HSCIF compatible UART,
- - "renesas,scif" for generic SCIF compatible UART.
- - "renesas,scifa" for generic SCIFA compatible UART.
- - "renesas,scifb" for generic SCIFB compatible UART.
- - "renesas,hscif" for generic HSCIF compatible UART.
- - "renesas,sci" for generic SCI compatible UART.
-
- When compatible with the generic version, nodes must list the
- SoC-specific version corresponding to the platform first, followed by the
- family-specific and/or generic versions.
-
- - reg: Base address and length of the I/O registers used by the UART.
- - interrupts: Must contain one or more interrupt-specifiers for the SCIx.
- If a single interrupt is expressed, then all events are
- multiplexed into this single interrupt.
-
- If multiple interrupts are provided by the hardware, the order
- in which the interrupts are listed must match order below. Note
- that some HW interrupt events may be muxed together resulting
- in duplicate entries.
- The interrupt order is as follows:
- 1. Error (ERI)
- 2. Receive buffer full (RXI)
- 3. Transmit buffer empty (TXI)
- 4. Break (BRI)
- 5. Data Ready (DRI)
- 6. Transmit End (TEI)
-
- - clocks: Must contain a phandle and clock-specifier pair for each entry
- in clock-names.
- - clock-names: Must contain "fck" for the SCIx UART functional clock.
- Apart from the divided functional clock, there may be other possible
- sources for the sampling clock, depending on SCIx variant.
- On (H)SCI(F) and some SCIFA, an additional clock may be specified:
- - "hsck" for the optional external clock input (on HSCIF),
- - "sck" for the optional external clock input (on other variants).
- On UARTs equipped with a Baud Rate Generator for External Clock (BRG)
- (some SCIF and HSCIF), additional clocks may be specified:
- - "brg_int" for the optional internal clock source for the frequency
- divider (typically the (AXI or SHwy) bus clock),
- - "scif_clk" for the optional external clock source for the frequency
- divider (SCIF_CLK).
-
-Note: Each enabled SCIx UART may have an optional "serialN" alias in the
-"aliases" node.
-
-Optional properties:
- - dmas: Must contain a list of two references to DMA specifiers, one for
- transmission, and one for reception.
- - dma-names: Must contain a list of two DMA names, "tx" and "rx".
- - {cts,dsr,dcd,rng,rts,dtr}-gpios: Specify GPIOs for modem lines, cfr. the
- generic serial DT bindings in serial.txt.
- - uart-has-rtscts: Indicates dedicated lines for RTS/CTS hardware flow
- control, cfr. the generic serial DT bindings in serial.txt.
-
-Example:
- aliases {
- serial0 = &scifa0;
- };
-
- scifa0: serial@e6c40000 {
- compatible = "renesas,scifa-r8a7790",
- "renesas,rcar-gen2-scifa", "renesas,scifa";
- reg = <0 0xe6c40000 0 64>;
- interrupt-parent = <&gic>;
- interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
- clock-names = "fck";
- dmas = <&dmac0 0x21>, <&dmac0 0x22>;
- dma-names = "tx", "rx";
- };
diff --git a/Documentation/devicetree/bindings/serial/renesas,sci.yaml b/Documentation/devicetree/bindings/serial/renesas,sci.yaml
new file mode 100644
index 000000000000..4183b7311f37
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/renesas,sci.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/serial/renesas,sci.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Renesas Serial Communication Interface
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+allOf:
+ - $ref: serial.yaml#
+
+properties:
+ compatible:
+ const: renesas,sci
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: Error interrupt
+ - description: Receive buffer full interrupt
+ - description: Transmit buffer empty interrupt
+ - description: Transmit end interrupt
+
+ interrupt-names:
+ items:
+ - const: eri
+ - const: rxi
+ - const: txi
+ - const: tei
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ enum:
+ - fck # UART functional clock
+ - sck # optional external clock input
+
+ uart-has-rtscts: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+examples:
+ - |
+ aliases {
+ serial0 = &sci0;
+ };
+
+ sci0: serial@ffff78 {
+ compatible = "renesas,sci";
+ reg = <0xffff78 8>;
+ interrupts = <88 0>, <89 0>, <90 0>, <91 0>;
+ clocks = <&fclk>;
+ clock-names = "fck";
+ };
diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
new file mode 100644
index 000000000000..70392b9bd977
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
@@ -0,0 +1,172 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/serial/renesas,scif.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Renesas Serial Communication Interface with FIFO (SCIF)
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+allOf:
+ - $ref: serial.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - renesas,scif-r7s72100 # RZ/A1H
+ - const: renesas,scif # generic SCIF compatible UART
+
+ - items:
+ - enum:
+ - renesas,scif-r7s9210 # RZ/A2
+
+ - items:
+ - enum:
+ - renesas,scif-r8a7778 # R-Car M1
+ - renesas,scif-r8a7779 # R-Car H1
+ - const: renesas,rcar-gen1-scif # R-Car Gen1
+ - const: renesas,scif # generic SCIF compatible UART
+
+ - items:
+ - enum:
+ - renesas,scif-r8a7743 # RZ/G1M
+ - renesas,scif-r8a7744 # RZ/G1N
+ - renesas,scif-r8a7745 # RZ/G1E
+ - renesas,scif-r8a77470 # RZ/G1C
+ - renesas,scif-r8a7790 # R-Car H2
+ - renesas,scif-r8a7791 # R-Car M2-W
+ - renesas,scif-r8a7792 # R-Car V2H
+ - renesas,scif-r8a7793 # R-Car M2-N
+ - renesas,scif-r8a7794 # R-Car E2
+ - const: renesas,rcar-gen2-scif # R-Car Gen2 and RZ/G1
+ - const: renesas,scif # generic SCIF compatible UART
+
+ - items:
+ - enum:
+ - renesas,scif-r8a774a1 # RZ/G2M
+ - renesas,scif-r8a774b1 # RZ/G2N
+ - renesas,scif-r8a774c0 # RZ/G2E
+ - renesas,scif-r8a7795 # R-Car H3
+ - renesas,scif-r8a7796 # R-Car M3-W
+ - renesas,scif-r8a77961 # R-Car M3-W+
+ - renesas,scif-r8a77965 # R-Car M3-N
+ - renesas,scif-r8a77970 # R-Car V3M
+ - renesas,scif-r8a77980 # R-Car V3H
+ - renesas,scif-r8a77990 # R-Car E3
+ - renesas,scif-r8a77995 # R-Car D3
+ - const: renesas,rcar-gen3-scif # R-Car Gen3 and RZ/G2
+ - const: renesas,scif # generic SCIF compatible UART
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ oneOf:
+ - items:
+ - description: A combined interrupt
+ - items:
+ - description: Error interrupt
+ - description: Receive buffer full interrupt
+ - description: Transmit buffer empty interrupt
+ - description: Transmit End interrupt
+ - items:
+ - description: Error interrupt
+ - description: Receive buffer full interrupt
+ - description: Transmit buffer empty interrupt
+ - description: Break interrupt
+ - description: Data Ready interrupt
+ - description: Transmit End interrupt
+
+ interrupt-names:
+ oneOf:
+ - items:
+ - const: eri
+ - const: rxi
+ - const: txi
+ - const: tei
+ - items:
+ - const: eri
+ - const: rxi
+ - const: txi
+ - const: bri
+ - const: dri
+ - const: tei
+
+ clocks:
+ minItems: 1
+ maxItems: 4
+
+ clock-names:
+ minItems: 1
+ maxItems: 4
+ items:
+ enum:
+ - fck # UART functional clock
+ - sck # optional external clock input
+ - brg_int # optional internal clock source for BRG frequency divider
+ - scif_clk # optional external clock source for BRG frequency divider
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ dmas:
+ description:
+ Must contain a list of pairs of references to DMA specifiers, one for
+ transmission, and one for reception.
+
+ dma-names:
+ minItems: 2
+ maxItems: 4
+ items:
+ enum:
+ - tx
+ - rx
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,rcar-gen2-scif
+ - renesas,rcar-gen3-scif
+then:
+ required:
+ - resets
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7791-sysc.h>
+ aliases {
+ serial0 = &scif0;
+ };
+
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
+ "renesas,scif";
+ reg = <0xe6e60000 64>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
+ <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 721>;
+ };
diff --git a/Documentation/devicetree/bindings/serial/renesas,scifa.yaml b/Documentation/devicetree/bindings/serial/renesas,scifa.yaml
new file mode 100644
index 000000000000..b28bcb268854
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/renesas,scifa.yaml
@@ -0,0 +1,107 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/serial/renesas,scifa.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Renesas Serial Communications Interface with FIFO A (SCIFA)
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+allOf:
+ - $ref: serial.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - renesas,scifa-r8a73a4 # R-Mobile APE6
+ - renesas,scifa-r8a7740 # R-Mobile A1
+ - renesas,scifa-sh73a0 # SH-Mobile AG5
+ - const: renesas,scifa # generic SCIFA compatible UART
+
+ - items:
+ - enum:
+ - renesas,scifa-r8a7743 # R8A7743 RZ/G1M
+ - renesas,scifa-r8a7744 # R8A7744 RZ/G1N
+ - renesas,scifa-r8a7745 # R8A7745 RZ/G1E
+ - renesas,scifa-r8a7790 # R8A7790 R-Car H2
+ - renesas,scifa-r8a7791 # R8A7791 R-Car M2-W
+ - renesas,scifa-r8a7793 # R8A7793 R-Car M2-N
+ - renesas,scifa-r8a7794 # R8A7794 R-Car E2
+ - const: renesas,rcar-gen2-scifa # R-Car Gen2 and RZ/G1
+ - const: renesas,scifa # generic SCIFA compatible UART
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ enum:
+ - fck # UART functional clock
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ dmas:
+ description:
+ Must contain a list of pairs of references to DMA specifiers, one for
+ transmission, and one for reception.
+
+ dma-names:
+ minItems: 2
+ maxItems: 4
+ items:
+ enum:
+ - tx
+ - rx
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,rcar-gen2-scifa
+then:
+ required:
+ - resets
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7790-sysc.h>
+ aliases {
+ serial0 = &scifa0;
+ };
+
+ scifa0: serial@e6c40000 {
+ compatible = "renesas,scifa-r8a7790", "renesas,rcar-gen2-scifa",
+ "renesas,scifa";
+ reg = <0xe6c40000 64>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 204>;
+ dmas = <&dmac0 0x21>, <&dmac0 0x22>, <&dmac1 0x21>, <&dmac1 0x22>;
+ dma-names = "tx", "rx", "tx", "rx";
+ };
diff --git a/Documentation/devicetree/bindings/serial/renesas,scifb.yaml b/Documentation/devicetree/bindings/serial/renesas,scifb.yaml
new file mode 100644
index 000000000000..57205cb1dcd4
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/renesas,scifb.yaml
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/serial/renesas,scifb.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Renesas Serial Communications Interface with FIFO B (SCIFB)
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+allOf:
+ - $ref: serial.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - renesas,scifb-r8a73a4 # R-Mobile APE6
+ - renesas,scifb-r8a7740 # R-Mobile A1
+ - renesas,scifb-sh73a0 # SH-Mobile AG5
+ - const: renesas,scifb # generic SCIFB compatible UART
+
+ - items:
+ - enum:
+ - renesas,scifb-r8a7743 # RZ/G1M
+ - renesas,scifb-r8a7744 # RZ/G1N
+ - renesas,scifb-r8a7745 # RZ/G1E
+ - renesas,scifb-r8a7790 # R-Car H2
+ - renesas,scifb-r8a7791 # R-Car M2-W
+ - renesas,scifb-r8a7793 # R-Car M2-N
+ - renesas,scifb-r8a7794 # R-Car E2
+ - const: renesas,rcar-gen2-scifb # R-Car Gen2 and RZ/G1
+ - const: renesas,scifb # generic SCIFB compatible UART
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ enum:
+ - fck # UART functional clock
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ dmas:
+ description:
+ Must contain a list of pairs of references to DMA specifiers, one for
+ transmission, and one for reception.
+
+ dma-names:
+ minItems: 2
+ maxItems: 4
+ items:
+ enum:
+ - tx
+ - rx
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,rcar-gen2-scifb
+then:
+ required:
+ - resets
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7740-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ scifb: serial@e6c30000 {
+ compatible = "renesas,scifb-r8a7740", "renesas,scifb";
+ reg = <0xe6c30000 0x100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
+ clock-names = "fck";
+ power-domains = <&pd_a3sp>;
+ };
diff --git a/Documentation/devicetree/bindings/serial/serial.txt b/Documentation/devicetree/bindings/serial/serial.txt
deleted file mode 100644
index 863c2893759e..000000000000
--- a/Documentation/devicetree/bindings/serial/serial.txt
+++ /dev/null
@@ -1,56 +0,0 @@
-Generic Serial DT Bindings
-
-This document lists a set of generic properties for describing UARTs in a
-device tree. Whether these properties apply to a particular device depends on
-the DT bindings for the actual device.
-
-Optional properties:
- - cts-gpios: Must contain a GPIO specifier, referring to the GPIO pin to be
- used as the UART's CTS line.
- - dcd-gpios: Must contain a GPIO specifier, referring to the GPIO pin to be
- used as the UART's DCD line.
- - dsr-gpios: Must contain a GPIO specifier, referring to the GPIO pin to be
- used as the UART's DSR line.
- - dtr-gpios: Must contain a GPIO specifier, referring to the GPIO pin to be
- used as the UART's DTR line.
- - rng-gpios: Must contain a GPIO specifier, referring to the GPIO pin to be
- used as the UART's RNG line.
- - rts-gpios: Must contain a GPIO specifier, referring to the GPIO pin to be
- used as the UART's RTS line.
-
- - uart-has-rtscts: The presence of this property indicates that the
- UART has dedicated lines for RTS/CTS hardware flow control, and that
- they are available for use (wired and enabled by pinmux configuration).
- This depends on both the UART hardware and the board wiring.
- Note that this property is mutually-exclusive with "cts-gpios" and
- "rts-gpios" above, unless support is provided to switch between modes
- dynamically.
-
-
-Examples:
-
- uart1: serial@48022000 {
- compatible = "ti,am3352-uart", "ti,omap3-uart";
- ti,hwmods = "uart2";
- clock-frequency = <48000000>;
- reg = <0x48022000 0x2000>;
- interrupts = <73>;
- dmas = <&edma 28 0>, <&edma 29 0>;
- dma-names = "tx", "rx";
- dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
- dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
- dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
- rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
- cts-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
- rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
- };
-
- scifa4: serial@e6c80000 {
- compatible = "renesas,scifa-sh73a0", "renesas,scifa";
- reg = <0xe6c80000 0x100>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
- clock-names = "fck";
- power-domains = <&pd_a3sp>;
- uart-has-rtscts;
- };
diff --git a/Documentation/devicetree/bindings/serial/serial.yaml b/Documentation/devicetree/bindings/serial/serial.yaml
new file mode 100644
index 000000000000..53204d90d0c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/serial.yaml
@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/serial/serial.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Serial Interface Generic DT Bindings
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+ - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+description:
+ This document lists a set of generic properties for describing UARTs in a
+ device tree. Whether these properties apply to a particular device depends
+ on the DT bindings for the actual device.
+
+ Each enabled UART may have an optional "serialN" alias in the "aliases" node,
+ where N is the port number (non-negative decimal integer) as printed on the
+ label next to the physical port.
+
+properties:
+ $nodename:
+ pattern: "^serial(@.*)?$"
+
+ cts-gpios:
+ maxItems: 1
+ description:
+ Must contain a GPIO specifier, referring to the GPIO pin to be used as
+ the UART's CTS line.
+
+ dcd-gpios:
+ maxItems: 1
+ description:
+ Must contain a GPIO specifier, referring to the GPIO pin to be used as
+ the UART's DCD line.
+
+ dsr-gpios:
+ maxItems: 1
+ description:
+ Must contain a GPIO specifier, referring to the GPIO pin to be used as
+ the UART's DSR line.
+
+ dtr-gpios:
+ maxItems: 1
+ description:
+ Must contain a GPIO specifier, referring to the GPIO pin to be used as
+ the UART's DTR line.
+
+ rng-gpios:
+ maxItems: 1
+ description:
+ Must contain a GPIO specifier, referring to the GPIO pin to be used as
+ the UART's RNG line.
+
+ rts-gpios:
+ maxItems: 1
+ description:
+ Must contain a GPIO specifier, referring to the GPIO pin to be used as
+ the UART's RTS line.
+
+ uart-has-rtscts:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ The presence of this property indicates that the UART has dedicated lines
+ for RTS/CTS hardware flow control, and that they are available for use
+ (wired and enabled by pinmux configuration). This depends on both the
+ UART hardware and the board wiring.
+
+if:
+ required:
+ - uart-has-rtscts
+then:
+ properties:
+ cts-gpios: false
+ rts-gpios: false
+
+patternProperties:
+ ".*":
+ if:
+ type: object
+ then:
+ description:
+ Serial attached devices shall be a child node of the host UART device
+ the slave device is attached to. It is expected that the attached
+ device is the only child node of the UART device. The slave device node
+ name shall reflect the generic type of device for the node.
+
+ properties:
+ compatible:
+ description:
+ Compatible of the device connected to the serial port.
+
+ max-speed:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The maximum baud rate the device operates at.
+ This should only be present if the maximum is less than the slave
+ device can support. For example, a particular board has some
+ signal quality issue or the host processor can't support higher
+ baud rates.
+
+ current-speed:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ The current baud rate the device operates at.
+ This should only be present in case a driver has no chance to know
+ the baud rate of the slave device.
+ Examples:
+ * device supports auto-baud
+ * the rate is setup by a bootloader and there is no way to reset
+ the device
+ * device baud rate is configured by its firmware but there is no
+ way to request the actual settings
+
+ required:
+ - compatible
+
+examples:
+ - |
+ serial@1234 {
+ compatible = "ns16550a";
+ reg = <0x1234 0x20>;
+ interrupts = <1>;
+
+ bluetooth {
+ compatible = "brcm,bcm43341-bt";
+ interrupt-parent = <&gpio>;
+ interrupts = <10>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/serial/slave-device.txt b/Documentation/devicetree/bindings/serial/slave-device.txt
deleted file mode 100644
index 40110e019620..000000000000
--- a/Documentation/devicetree/bindings/serial/slave-device.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-Serial Slave Device DT binding
-
-This documents the binding structure and common properties for serial
-attached devices. Common examples include Bluetooth, WiFi, NFC and GPS
-devices.
-
-Serial attached devices shall be a child node of the host UART device the
-slave device is attached to. It is expected that the attached device is
-the only child node of the UART device. The slave device node name shall
-reflect the generic type of device for the node.
-
-Required Properties:
-
-- compatible : A string reflecting the vendor and specific device the node
- represents.
-
-Optional Properties:
-
-- max-speed : The maximum baud rate the device operates at. This should
- only be present if the maximum is less than the slave device
- can support. For example, a particular board has some signal
- quality issue or the host processor can't support higher
- baud rates.
-- current-speed : The current baud rate the device operates at. This should
- only be present in case a driver has no chance to know
- the baud rate of the slave device.
- Examples:
- * device supports auto-baud
- * the rate is setup by a bootloader and there is no
- way to reset the device
- * device baud rate is configured by its firmware but
- there is no way to request the actual settings
-
-Example:
-
-serial@1234 {
- compatible = "ns16550a";
- interrupts = <1>;
-
- bluetooth {
- compatible = "brcm,bcm43341-bt";
- interrupt-parent = <&gpio>;
- interrupts = <10>;
- };
-};
diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
index b42002542690..b962f8db4ce9 100644
--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
@@ -27,6 +27,7 @@ properties:
- rockchip,rk3066-uart
- rockchip,rk3188-uart
- rockchip,rk3288-uart
+ - rockchip,rk3308-uart
- rockchip,rk3328-uart
- rockchip,rk3368-uart
- rockchip,rk3399-uart
diff --git a/Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml b/Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml
new file mode 100644
index 000000000000..09a30300850c
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/socionext,uniphier-uart.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UniPhier UART controller
+
+maintainers:
+ - Masahiro Yamada <yamada.masahiro@socionext.com>
+
+properties:
+ compatible:
+ const: socionext,uniphier-uart
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+
+ auto-flow-control:
+ description: enable automatic flow control support.
+ $ref: /schemas/types.yaml#/definitions/flag
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+examples:
+ - |
+ aliases {
+ serial0 = &serial0;
+ };
+
+ serial0: serial@54006800 {
+ compatible = "socionext,uniphier-uart";
+ reg = <0x54006800 0x40>;
+ interrupts = <0 33 4>;
+ clocks = <&uart_clk>;
+ };
diff --git a/Documentation/devicetree/bindings/serial/uniphier-uart.txt b/Documentation/devicetree/bindings/serial/uniphier-uart.txt
deleted file mode 100644
index 7a1bf02bb869..000000000000
--- a/Documentation/devicetree/bindings/serial/uniphier-uart.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-UniPhier UART controller
-
-Required properties:
-- compatible: should be "socionext,uniphier-uart".
-- reg: offset and length of the register set for the device.
-- interrupts: a single interrupt specifier.
-- clocks: phandle to the input clock.
-
-Optional properties:
--auto-flow-control: enable automatic flow control support.
-
-Example:
- aliases {
- serial0 = &serial0;
- };
-
- serial0: serial@54006800 {
- compatible = "socionext,uniphier-uart";
- reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
- clocks = <&uart_clk>;
- };
diff --git a/Documentation/devicetree/bindings/soc/amlogic/amlogic,canvas.yaml b/Documentation/devicetree/bindings/soc/amlogic/amlogic,canvas.yaml
index f548594d020b..cb008fd188d8 100644
--- a/Documentation/devicetree/bindings/soc/amlogic/amlogic,canvas.yaml
+++ b/Documentation/devicetree/bindings/soc/amlogic/amlogic,canvas.yaml
@@ -40,6 +40,8 @@ required:
- compatible
- reg
+additionalProperties: false
+
examples:
- |
canvas: video-lut@48 {
diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,aips-bus.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,aips-bus.yaml
new file mode 100644
index 000000000000..3cbf2d28a188
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,aips-bus.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,aips-bus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: i.MX AHB to IP Bridge
+
+maintainers:
+ - Peng Fan <peng.fan@nxp.com>
+
+description: |
+ This particular peripheral is designed as the bridge between
+ AHB bus and peripherals with the lower bandwidth IP Slave (IPS)
+ buses.
+
+select:
+ properties:
+ compatible:
+ contains:
+ const: fsl,aips-bus
+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - const: fsl,aips-bus
+ - const: simple-bus
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ bus@30000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x30000000 0x400000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ };
+...
diff --git a/Documentation/devicetree/bindings/sound/adi,adau7118.yaml b/Documentation/devicetree/bindings/sound/adi,adau7118.yaml
index 75e0cbe6be70..76ee695097bf 100644
--- a/Documentation/devicetree/bindings/sound/adi,adau7118.yaml
+++ b/Documentation/devicetree/bindings/sound/adi,adau7118.yaml
@@ -59,6 +59,8 @@ required:
- iovdd-supply
- dvdd-supply
+additionalProperties: false
+
examples:
- |
i2c {
diff --git a/Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml b/Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml
index 38eaf0c028f9..a495d5fc0d23 100644
--- a/Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml
+++ b/Documentation/devicetree/bindings/sound/qcom,wcd934x.yaml
@@ -139,6 +139,8 @@ required:
- "#address-cells"
- "#size-cells"
+additionalProperties: false
+
examples:
- |
codec@1,0{
diff --git a/Documentation/devicetree/bindings/sound/renesas,fsi.yaml b/Documentation/devicetree/bindings/sound/renesas,fsi.yaml
index 140a37fc3c0b..d1b65554e681 100644
--- a/Documentation/devicetree/bindings/sound/renesas,fsi.yaml
+++ b/Documentation/devicetree/bindings/sound/renesas,fsi.yaml
@@ -63,6 +63,8 @@ required:
- reg
- interrupts
+additionalProperties: false
+
examples:
- |
sh_fsi2: sound@ec230000 {
diff --git a/Documentation/devicetree/bindings/sound/samsung,odroid.yaml b/Documentation/devicetree/bindings/sound/samsung,odroid.yaml
index c6b244352d05..8ff2d39e7d17 100644
--- a/Documentation/devicetree/bindings/sound/samsung,odroid.yaml
+++ b/Documentation/devicetree/bindings/sound/samsung,odroid.yaml
@@ -69,6 +69,8 @@ required:
- cpu
- codec
+additionalProperties: false
+
examples:
- |
sound {
diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.yaml b/Documentation/devicetree/bindings/sound/samsung-i2s.yaml
index 53e3bad4178c..b2ad093d94df 100644
--- a/Documentation/devicetree/bindings/sound/samsung-i2s.yaml
+++ b/Documentation/devicetree/bindings/sound/samsung-i2s.yaml
@@ -115,6 +115,8 @@ required:
- clocks
- clock-names
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/clock/exynos-audss-clk.h>
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt
deleted file mode 100644
index 1d64b61f5171..000000000000
--- a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-Qualcomm Quad Serial Peripheral Interface (QSPI)
-
-The QSPI controller allows SPI protocol communication in single, dual, or quad
-wire transmission modes for read/write access to slaves such as NOR flash.
-
-Required properties:
-- compatible: An SoC specific identifier followed by "qcom,qspi-v1", such as
- "qcom,sdm845-qspi", "qcom,qspi-v1"
-- reg: Should contain the base register location and length.
-- interrupts: Interrupt number used by the controller.
-- clocks: Should contain the core and AHB clock.
-- clock-names: Should be "core" for core clock and "iface" for AHB clock.
-
-SPI slave nodes must be children of the SPI master node and can contain
-properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
-
-Example:
-
- qspi: spi@88df000 {
- compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
- reg = <0x88df000 0x600>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "iface", "core";
- clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
- <&gcc GCC_QSPI_CORE_CLK>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <25000000>;
- spi-tx-bus-width = <2>;
- spi-rx-bus-width = <2>;
- };
- };
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml
new file mode 100644
index 000000000000..0cf470eaf2a0
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm Quad Serial Peripheral Interface (QSPI)
+
+maintainers:
+ - Mukesh Savaliya <msavaliy@codeaurora.org>
+ - Akash Asthana <akashast@codeaurora.org>
+
+description:
+ The QSPI controller allows SPI protocol communication in single, dual, or quad
+ wire transmission modes for read/write access to slaves such as NOR flash.
+
+allOf:
+ - $ref: /spi/spi-controller.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sdm845-qspi
+ - const: qcom,qspi-v1
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: iface
+ - const: core
+
+ clocks:
+ items:
+ - description: AHB clock
+ - description: QSPI core clock
+
+ interconnects:
+ minItems: 1
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: qspi-config
+ - const: qspi-memory
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clock-names
+ - clocks
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc: soc@0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ qspi: spi@88df000 {
+ compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
+ reg = <0 0x88df000 0 0x600>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "iface", "core";
+ clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+ <&gcc GCC_QSPI_CORE_CLK>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ };
+
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml b/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
index 222990f9923c..930188bc5e6a 100644
--- a/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
+++ b/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
@@ -43,6 +43,9 @@ properties:
'#size-cells':
const: 1
+ ranges:
+ maxItems: 1
+
required:
- compatible
- reg
@@ -51,9 +54,12 @@ required:
- clock-names
- '#address-cells'
- '#size-cells'
+ - ranges
+
+additionalProperties: false
patternProperties:
- "^.+-sram$":
+ "-sram@[0-9a-f]+$":
type: object
description: A region of reserved memory.
@@ -61,12 +67,8 @@ patternProperties:
reg:
maxItems: 1
- ranges:
- maxItems: 1
-
required:
- reg
- - ranges
examples:
- |
@@ -88,9 +90,9 @@ examples:
#address-cells = <1>;
#size-cells = <1>;
+ ranges = <0 0xfec00000 0x100000>;
gmu-sram@0 {
reg = <0x0 0x100000>;
- ranges = <0 0 0xfec00000 0x100000>;
};
};
diff --git a/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml b/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml
index f761681e4c0d..e43ec50bda37 100644
--- a/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml
+++ b/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml
@@ -32,6 +32,8 @@ properties:
description: phandle to the ao-secure syscon
$ref: '/schemas/types.yaml#/definitions/phandle'
+ '#thermal-sensor-cells':
+ const: 0
required:
- compatible
@@ -40,6 +42,8 @@ required:
- clocks
- amlogic,ao-secure
+additionalProperties: false
+
examples:
- |
cpu_temp: temperature-sensor@ff634800 {
diff --git a/Documentation/devicetree/bindings/thermal/armada-thermal.txt b/Documentation/devicetree/bindings/thermal/armada-thermal.txt
index f3b441100890..b0bee7e42038 100644
--- a/Documentation/devicetree/bindings/thermal/armada-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/armada-thermal.txt
@@ -12,7 +12,7 @@ Required properties:
Note: these bindings are deprecated for AP806/CP110 and should instead
follow the rules described in:
-Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
+Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt
- reg: Device's register space.
diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
index eef13b9446a8..a57b76ad7dea 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
+++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
@@ -47,19 +47,30 @@ properties:
- description: TM registers
- description: SROT registers
+ interrupts:
+ minItems: 1
+ items:
+ - description: Combined interrupt if upper or lower threshold crossed
+ - description: Interrupt if critical threshold crossed
+
+ interrupt-names:
+ minItems: 1
+ items:
+ - const: uplow
+ - const: critical
+
nvmem-cells:
minItems: 1
maxItems: 2
description:
Reference to an nvmem node for the calibration data
- nvmem-cells-names:
+ nvmem-cell-names:
minItems: 1
maxItems: 2
items:
- - enum:
- - caldata
- - calsel
+ - const: calib
+ - const: calib_sel
"#qcom,sensors":
allOf:
@@ -90,22 +101,16 @@ allOf:
then:
properties:
interrupts:
- items:
- - description: Combined interrupt if upper or lower threshold crossed
+ maxItems: 1
interrupt-names:
- items:
- - const: uplow
+ maxItems: 1
else:
properties:
interrupts:
- items:
- - description: Combined interrupt if upper or lower threshold crossed
- - description: Interrupt if critical threshold crossed
+ minItems: 2
interrupt-names:
- items:
- - const: uplow
- - const: critical
+ minItems: 2
required:
- compatible
@@ -115,6 +120,8 @@ required:
- interrupt-names
- "#thermal-sensor-cells"
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -125,7 +132,7 @@ examples:
<0x4a8000 0x1000>; /* SROT */
nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
- nvmem-cell-names = "caldata", "calsel";
+ nvmem-cell-names = "calib", "calib_sel";
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow";
diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
deleted file mode 100644
index 196112d23b1e..000000000000
--- a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
+++ /dev/null
@@ -1,78 +0,0 @@
-* Renesas R-Car Thermal
-
-Required properties:
-- compatible : "renesas,thermal-<soctype>",
- "renesas,rcar-gen2-thermal" (with thermal-zone) or
- "renesas,rcar-thermal" (without thermal-zone) as
- fallback except R-Car V3M/E3/D3 and RZ/G2E.
- Examples with soctypes are:
- - "renesas,thermal-r8a73a4" (R-Mobile APE6)
- - "renesas,thermal-r8a7743" (RZ/G1M)
- - "renesas,thermal-r8a7744" (RZ/G1N)
- - "renesas,thermal-r8a774c0" (RZ/G2E)
- - "renesas,thermal-r8a7779" (R-Car H1)
- - "renesas,thermal-r8a7790" (R-Car H2)
- - "renesas,thermal-r8a7791" (R-Car M2-W)
- - "renesas,thermal-r8a7792" (R-Car V2H)
- - "renesas,thermal-r8a7793" (R-Car M2-N)
- - "renesas,thermal-r8a77970" (R-Car V3M)
- - "renesas,thermal-r8a77990" (R-Car E3)
- - "renesas,thermal-r8a77995" (R-Car D3)
-- reg : Address range of the thermal registers.
- The 1st reg will be recognized as common register
- if it has "interrupts".
-
-Option properties:
-
-- interrupts : If present should contain 3 interrupts for
- R-Car V3M/E3/D3 and RZ/G2E or 1 interrupt otherwise.
-
-Example (non interrupt support):
-
-thermal@ffc48000 {
- compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
- reg = <0xffc48000 0x38>;
-};
-
-Example (interrupt support):
-
-thermal@e61f0000 {
- compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
- reg = <0xe61f0000 0x14
- 0xe61f0100 0x38
- 0xe61f0200 0x38
- 0xe61f0300 0x38>;
- interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-Example (with thermal-zone):
-
-thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <1000>;
- polling-delay = <5000>;
-
- thermal-sensors = <&thermal>;
-
- trips {
- cpu-crit {
- temperature = <115000>;
- hysteresis = <0>;
- type = "critical";
- };
- };
- cooling-maps {
- };
- };
-};
-
-thermal: thermal@e61f0000 {
- compatible = "renesas,thermal-r8a7790",
- "renesas,rcar-gen2-thermal",
- "renesas,rcar-thermal";
- reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
- interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
- power-domains = <&cpg_clocks>;
- #thermal-sensor-cells = <0>;
-};
diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.yaml b/Documentation/devicetree/bindings/thermal/rcar-thermal.yaml
new file mode 100644
index 000000000000..d2f4f1b063ac
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/rcar-thermal.yaml
@@ -0,0 +1,139 @@
+# SPDX-License-Identifier: GPL-2.0-only
+# Copyright (C) 2020 Renesas Electronics Corp.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/rcar-thermal.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car Thermal
+
+maintainers:
+ - Niklas Söderlund <niklas.soderlund@ragnatech.se>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - renesas,thermal-r8a73a4 # R-Mobile APE6
+ - renesas,thermal-r8a7779 # R-Car H1
+ - const: renesas,rcar-thermal # Generic without thermal-zone
+ - items:
+ - enum:
+ - renesas,thermal-r8a7743 # RZ/G1M
+ - renesas,thermal-r8a7744 # RZ/G1N
+ - const: renesas,rcar-gen2-thermal # Generic thermal-zone
+ - items:
+ - enum:
+ - renesas,thermal-r8a7790 # R-Car H2
+ - renesas,thermal-r8a7791 # R-Car M2-W
+ - renesas,thermal-r8a7792 # R-Car V2H
+ - renesas,thermal-r8a7793 # R-Car M2-N
+ - const: renesas,rcar-gen2-thermal # Generic thermal-zone
+ - const: renesas,rcar-thermal # Generic without thermal-zone
+ - items:
+ - enum:
+ - renesas,thermal-r8a774c0 # RZ/G2E
+ - renesas,thermal-r8a77970 # R-Car V3M
+ - renesas,thermal-r8a77990 # R-Car E3
+ - renesas,thermal-r8a77995 # R-Car D3
+ reg:
+ description:
+ Address ranges of the thermal registers. If more then one range is given
+ the first one must be the common registers followed by each sensor
+ according the the datasheet.
+ minItems: 1
+ maxItems: 4
+
+ interrupts:
+ minItems: 1
+ maxItems: 3
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,thermal-r8a73a4 # R-Mobile APE6
+ - renesas,thermal-r8a7779 # R-Car H1
+then:
+ required:
+ - compatible
+ - reg
+else:
+ required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - power-domains
+ - resets
+
+examples:
+ # Example (non interrupt support)
+ - |
+ thermal@ffc48000 {
+ compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
+ reg = <0xffc48000 0x38>;
+ };
+
+ # Example (interrupt support)
+ - |
+ #include <dt-bindings/clock/r8a73a4-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ thermal@e61f0000 {
+ compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
+ reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
+ <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
+ power-domains = <&pd_c5>;
+ };
+
+ # Example (with thermal-zone)
+ - |
+ #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7790-sysc.h>
+
+ thermal: thermal@e61f0000 {
+ compatible = "renesas,thermal-r8a7790",
+ "renesas,rcar-gen2-thermal",
+ "renesas,rcar-thermal";
+ reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 522>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 522>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ cooling-maps {
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
index 6deead07728e..fa255672e8e5 100644
--- a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
+++ b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
@@ -82,6 +82,8 @@ properties:
required:
- compatible
+additionalProperties: false
+
oneOf:
- required:
- interrupts
diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml
index 102f319833d9..582bbef62b95 100644
--- a/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml
+++ b/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml
@@ -32,6 +32,8 @@ properties:
'#size-cells':
const: 1
+ ranges: true
+
clock-frequency:
description: The frequency of the main counter, in Hz. Should be present
only where necessary to work around broken firmware which does not configure
@@ -93,6 +95,8 @@ required:
- '#address-cells'
- '#size-cells'
+additionalProperties: false
+
examples:
- |
timer@f0000000 {
diff --git a/Documentation/devicetree/bindings/timer/arm,global_timer.yaml b/Documentation/devicetree/bindings/timer/arm,global_timer.yaml
index 21c24a8e28fd..4956c8f409d2 100644
--- a/Documentation/devicetree/bindings/timer/arm,global_timer.yaml
+++ b/Documentation/devicetree/bindings/timer/arm,global_timer.yaml
@@ -35,6 +35,8 @@ required:
- reg
- clocks
+additionalProperties: false
+
examples:
- |
timer@2c000600 {
diff --git a/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml b/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml
index 2807225db902..1a721d8af67a 100644
--- a/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml
@@ -32,6 +32,8 @@ required:
- reg
- interrupts
+additionalProperties: false
+
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml
index 273e359854dd..37bd01a62c52 100644
--- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml
+++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml
@@ -52,6 +52,8 @@ required:
- interrupts
- reg
+additionalProperties: false
+
examples:
- |
// In this example, the IP contains two local timers, using separate
diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml
index 330cab25cc92..4165352a590a 100644
--- a/Documentation/devicetree/bindings/trivial-devices.yaml
+++ b/Documentation/devicetree/bindings/trivial-devices.yaml
@@ -34,10 +34,6 @@ properties:
- adi,adt7461
# +/-1C TDM Extended Temp Range I.C
- adt7461
- # Three-Axis Digital Accelerometer
- - adi,adxl345
- # Three-Axis Digital Accelerometer (backward-compatibility value "adi,adxl345" must be listed too)
- - adi,adxl346
# AMS iAQ-Core VOC Sensor
- ams,iaq-core
# i2c serial eeprom (24cxx)
@@ -367,4 +363,6 @@ required:
- compatible
- reg
+additionalProperties: false
+
...
diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml
index 6baf00e7d0a9..0d6d850a7f17 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.yaml
+++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
@@ -32,20 +32,19 @@ properties:
- const: lantiq,arx100-usb
- const: lantiq,xrx200-usb
- items:
- - const: amlogic,meson8-usb
- - const: snps,dwc2
- - items:
- - const: amlogic,meson8b-usb
- - const: snps,dwc2
- - const: amlogic,meson-gxbb-usb
- - items:
- - const: amlogic,meson-g12a-usb
+ - enum:
+ - amlogic,meson8-usb
+ - amlogic,meson8b-usb
+ - amlogic,meson-gxbb-usb
+ - amlogic,meson-g12a-usb
- const: snps,dwc2
- const: amcc,dwc-otg
- const: snps,dwc2
- const: st,stm32f4x9-fsotg
- const: st,stm32f4x9-hsotg
- const: st,stm32f7-hsotg
+ - const: st,stm32mp15-fsotg
+ - const: st,stm32mp15-hsotg
- const: samsung,s3c6400-hsotg
reg:
@@ -91,6 +90,10 @@ properties:
vusb_a-supply:
description: phandle to voltage regulator of analog section.
+ vusb33d-supply:
+ description: reference to the VBUS and ID sensing comparators supply, in
+ order to perform OTG operation, used on STM32MP15 SoCs.
+
dr_mode:
enum: [host, peripheral, otg]
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt
index 66c394f9e11f..6aae1544f240 100644
--- a/Documentation/devicetree/bindings/usb/exynos-usb.txt
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -78,7 +78,14 @@ Required properties:
- ranges: allows valid 1:1 translation between child's address space and
parent's address space
- clocks: Clock IDs array as required by the controller.
- - clock-names: names of clocks correseponding to IDs in the clock property
+ - clock-names: Names of clocks corresponding to IDs in the clock property.
+ Following clock names shall be provided for different
+ compatibles:
+ - samsung,exynos5250-dwusb3: "usbdrd30",
+ - samsung,exynos5433-dwusb3: "aclk", "susp_clk", "pipe_pclk",
+ "phyclk",
+ - samsung,exynos7-dwusb3: "usbdrd30", "usbdrd30_susp_clk",
+ "usbdrd30_axius_clk"
- vdd10-supply: 1.0V powr supply
- vdd33-supply: 3.0V/3.3V power supply
diff --git a/Documentation/devicetree/bindings/usb/fcs,fusb302.txt b/Documentation/devicetree/bindings/usb/fcs,fusb302.txt
index ba2e32d500c0..60e4654297af 100644
--- a/Documentation/devicetree/bindings/usb/fcs,fusb302.txt
+++ b/Documentation/devicetree/bindings/usb/fcs,fusb302.txt
@@ -9,7 +9,7 @@ Required sub-node:
- connector : The "usb-c-connector" attached to the FUSB302 IC. The bindings
of the connector node are specified in:
- Documentation/devicetree/bindings/connector/usb-connector.txt
+ Documentation/devicetree/bindings/connector/usb-connector.yaml
Example:
diff --git a/Documentation/devicetree/bindings/usb/generic.txt b/Documentation/devicetree/bindings/usb/generic.txt
index 67c51759a642..ba472e7aefc9 100644
--- a/Documentation/devicetree/bindings/usb/generic.txt
+++ b/Documentation/devicetree/bindings/usb/generic.txt
@@ -34,7 +34,7 @@ Optional properties:
- usb-role-switch: boolean, indicates that the device is capable of assigning
the USB data role (USB host or USB device) for a given
USB connector, such as Type-C, Type-B(micro).
- see connector/usb-connector.txt.
+ see connector/usb-connector.yaml.
- role-switch-default-mode: indicating if usb-role-switch is enabled, the
device default operation mode of controller while usb
role is USB_ROLE_NONE. Valid arguments are "host" and
diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
index e0ae6096f7ac..a82ca438aec1 100644
--- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
+++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
@@ -34,7 +34,7 @@ Optional properties:
dual-role mode.
it's considered valid for compatibility reasons, not allowed for
new bindings, and put into a usb-connector node.
- see connector/usb-connector.txt.
+ see connector/usb-connector.yaml.
- pinctrl-names : a pinctrl state named "default" is optional, and need be
defined if auto drd switch is enabled, that means the property dr_mode
is set as "otg", and meanwhile the property "mediatek,enable-manual-drd"
diff --git a/Documentation/devicetree/bindings/usb/mediatek,musb.txt b/Documentation/devicetree/bindings/usb/mediatek,musb.txt
index 2b8a87c90d9e..5eedb0296562 100644
--- a/Documentation/devicetree/bindings/usb/mediatek,musb.txt
+++ b/Documentation/devicetree/bindings/usb/mediatek,musb.txt
@@ -23,7 +23,7 @@ Optional properties:
MTCMOS
Required child nodes:
- usb connector node as defined in bindings/connector/usb-connector.txt
+ usb connector node as defined in bindings/connector/usb-connector.yaml
Optional properties:
- id-gpios : input GPIO for USB ID pin.
- vbus-gpios : input GPIO for USB VBUS pin.
diff --git a/Documentation/devicetree/bindings/usb/richtek,rt1711h.txt b/Documentation/devicetree/bindings/usb/richtek,rt1711h.txt
index e3fc57e605ed..6f8115db2ea9 100644
--- a/Documentation/devicetree/bindings/usb/richtek,rt1711h.txt
+++ b/Documentation/devicetree/bindings/usb/richtek,rt1711h.txt
@@ -9,7 +9,7 @@ Required properties:
Required sub-node:
- connector: The "usb-c-connector" attached to the tcpci chip, the bindings
of connector node are specified in
- Documentation/devicetree/bindings/connector/usb-connector.txt
+ Documentation/devicetree/bindings/connector/usb-connector.yaml
Example :
rt1711h@4e {
diff --git a/Documentation/devicetree/bindings/usb/ti,hd3ss3220.txt b/Documentation/devicetree/bindings/usb/ti,hd3ss3220.txt
index 25780e945b15..2bd21b22ce95 100644
--- a/Documentation/devicetree/bindings/usb/ti,hd3ss3220.txt
+++ b/Documentation/devicetree/bindings/usb/ti,hd3ss3220.txt
@@ -9,7 +9,7 @@ Required sub-node:
- connector: The "usb-c-connector" attached to the hd3ss3220 chip. The
bindings of the connector node are specified in:
- Documentation/devicetree/bindings/connector/usb-connector.txt
+ Documentation/devicetree/bindings/connector/usb-connector.yaml
Example:
hd3ss3220@47 {
diff --git a/Documentation/devicetree/bindings/usb/typec-tcpci.txt b/Documentation/devicetree/bindings/usb/typec-tcpci.txt
index 0dd1469e7318..2082522b1c32 100644
--- a/Documentation/devicetree/bindings/usb/typec-tcpci.txt
+++ b/Documentation/devicetree/bindings/usb/typec-tcpci.txt
@@ -13,7 +13,7 @@ Required properties:
Required sub-node:
- connector: The "usb-c-connector" attached to the tcpci chip, the bindings
of connector node are specified in
- Documentation/devicetree/bindings/connector/usb-connector.txt
+ Documentation/devicetree/bindings/connector/usb-connector.yaml
Example:
diff --git a/Documentation/devicetree/bindings/usb/usb-conn-gpio.txt b/Documentation/devicetree/bindings/usb/usb-conn-gpio.txt
index 3d05ae56cb0d..ec80641208a5 100644
--- a/Documentation/devicetree/bindings/usb/usb-conn-gpio.txt
+++ b/Documentation/devicetree/bindings/usb/usb-conn-gpio.txt
@@ -8,11 +8,11 @@ Required properties:
- compatible : should include "gpio-usb-b-connector" and "usb-b-connector".
- id-gpios, vbus-gpios : input gpios, either one of them must be present,
and both can be present as well.
- see connector/usb-connector.txt
+ see connector/usb-connector.yaml
Optional properties:
- vbus-supply : can be present if needed when supports dual role mode.
- see connector/usb-connector.txt
+ see connector/usb-connector.yaml
- Sub-nodes:
- port : can be present.
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 49467b58913f..d3891386d671 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -141,6 +141,8 @@ patternProperties:
description: Shenzhen AZW Technology Co., Ltd.
"^bananapi,.*":
description: BIPAI KEJI LIMITED
+ "^beacon,.*":
+ description: Compass Electronics Group, LLC
"^bhf,.*":
description: Beckhoff Automation GmbH & Co. KG
"^bitmain,.*":
@@ -235,6 +237,8 @@ patternProperties:
description: DataImage, Inc.
"^davicom,.*":
description: DAVICOM Semiconductor, Inc.
+ "^dell,.*":
+ description: Dell Inc.
"^delta,.*":
description: Delta Electronics, Inc.
"^denx,.*":
@@ -289,6 +293,8 @@ patternProperties:
description: Elan Microelectronic Corp.
"^elgin,.*":
description: Elgin S/A.
+ "^elida,.*":
+ description: Shenzhen Elida Technology Co., Ltd.
"^embest,.*":
description: Shenzhen Embest Technology Co., Ltd.
"^emlid,.*":
@@ -301,6 +307,8 @@ patternProperties:
description: emtrion GmbH
"^endless,.*":
description: Endless Mobile, Inc.
+ "^ene,.*":
+ description: ENE Technology, Inc.
"^energymicro,.*":
description: Silicon Laboratories (formerly Energy Micro AS)
"^engicam,.*":
@@ -479,6 +487,8 @@ patternProperties:
description: Intersil
"^issi,.*":
description: Integrated Silicon Solutions Inc.
+ "^ite,.*":
+ description: ITE Tech, Inc.
"^itead,.*":
description: ITEAD Intelligent Systems Co.Ltd
"^iwave,.*":
@@ -555,6 +565,8 @@ patternProperties:
description: LinkSprite Technologies, Inc.
"^linksys,.*":
description: Belkin International, Inc. (Linksys)
+ "^linutronix,.*":
+ description: Linutronix GmbH
"^linux,.*":
description: Linux-specific binding
"^linx,.*":
@@ -641,6 +653,9 @@ patternProperties:
description: Monolithic Power Systems Inc.
"^mqmaker,.*":
description: mqmaker Inc.
+ "^mrvl,.*":
+ description: Marvell Technology Group Ltd.
+ deprecated: true
"^mscc,.*":
description: Microsemi Corporation
"^msi,.*":
@@ -741,6 +756,8 @@ patternProperties:
description: OmniVision Technologies
"^oxsemi,.*":
description: Oxford Semiconductor, Ltd.
+ "^ozzmaker,.*":
+ description: OzzMaker
"^panasonic,.*":
description: Panasonic Corporation
"^parade,.*":
@@ -775,6 +792,8 @@ patternProperties:
description: Broadcom Corporation (formerly PLX Technology)
"^pni,.*":
description: PNI Sensor Corporation
+ "^pocketbook,.*":
+ description: PocketBook International SA
"^polaroid,.*":
description: Polaroid Corporation
"^portwell,.*":
@@ -873,6 +892,8 @@ patternProperties:
description: Small Form Factor Committee
"^sgd,.*":
description: Solomon Goldentek Display Corporation
+ "^sgmicro,.*":
+ description: SG Micro Corp
"^sgx,.*":
description: SGX Sensortech
"^sharp,.*":
@@ -996,6 +1017,8 @@ patternProperties:
"^toppoly,.*":
description: TPO (deprecated, use tpo)
deprecated: true
+ "^topwise,.*":
+ description: Topwise Communication Co., Ltd.
"^toradex,.*":
description: Toradex AG
"^toshiba,.*":
@@ -1066,6 +1089,8 @@ patternProperties:
description: Vision Optical Technology Co., Ltd.
"^vxt,.*":
description: VXT Ltd
+ "^waveshare,.*":
+ description: Waveshare Electronics
"^wd,.*":
description: Western Digital Corp.
"^wetek,.*":
@@ -1092,6 +1117,8 @@ patternProperties:
description: X-Powers
"^xes,.*":
description: Extreme Engineering Solutions (X-ES)
+ "^xiaomi,.*":
+ description: Xiaomi Technology Co., Ltd.
"^xillybus,.*":
description: Xillybus Ltd.
"^xinpeng,.*":
diff --git a/Documentation/devicetree/bindings/watchdog/st,stpmic1-wdt.txt b/Documentation/devicetree/bindings/watchdog/st,stpmic1-wdt.txt
deleted file mode 100644
index 7cc1407f15cb..000000000000
--- a/Documentation/devicetree/bindings/watchdog/st,stpmic1-wdt.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-STMicroelectronics STPMIC1 Watchdog
-
-Required properties:
-
-- compatible : should be "st,stpmic1-wdt"
-
-Example:
-
-watchdog {
- compatible = "st,stpmic1-wdt";
-};