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authorLinus Torvalds <torvalds@linux-foundation.org>2015-09-01 21:55:57 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2015-09-01 21:55:57 +0300
commit28dce7c7703fd6ec922fa63b1187cf9f43d1d1c4 (patch)
tree4b0d35871c136a3e5247483beac0a2108c8d68f6 /Documentation
parent361f7d175734a8e21bcd0585eca9be195c12c5c5 (diff)
parent3d5926599a6bc551efc0c8b244469a711f0d0166 (diff)
downloadlinux-28dce7c7703fd6ec922fa63b1187cf9f43d1d1c4.tar.xz
Merge tag 'arc-4.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC architecture updates from Vineet Gupta: "ARC updates for 4.3: - perf support for ARCv2 based cores (sampling interrupt, SMP) - leftovers for ARCv2 support - futex fixes" * tag 'arc-4.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARCv2: entry: Fix reserved handler ARCv2: perf: Finally introduce HS perf unit ARCv2: perf: SMP support ARCv2: perf: implement exclusion of event counting in user or kernel mode ARCv2: perf: Support sampling events using overflow interrupts ARCv2: perf: implement "event_set_period" ARC: perf: cap the number of counters to hardware max of 32 ARC: Eliminate some ARCv2 specific code for ARCompact build ARC: add/fix some comments in code - no functional change ARC: change some branchs to jumps to resolve linkage errors ARC: ensure futex ops are atomic in !LLSC config ARC: Enable HAVE_FUTEX_CMPXCHG ARC: make futex_atomic_cmpxchg_inatomic() return bimodal ARC: futex cosmetics ARC: add barriers to futex code ARCv2: IOC: Allow boot time disable ARCv2: SLC: Allow boot time disable ARCv2: Support IO Coherency and permutations involving L1 and L2 caches ARC: Enable optimistic spinning for LLSC config MAINTAINERS: add git tree for the arc architecture
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/arc/archs-pct.txt17
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diff --git a/Documentation/devicetree/bindings/arc/archs-pct.txt b/Documentation/devicetree/bindings/arc/archs-pct.txt
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+* ARC HS Performance Counters
+
+The ARC HS can be configured with a pipeline performance monitor for counting
+CPU and cache events like cache misses and hits. Like conventional PCT there
+are 100+ hardware conditions dynamically mapped to upto 32 counters.
+It also supports overflow interrupts.
+
+Required properties:
+
+- compatible : should contain
+ "snps,archs-pct"
+
+Example:
+
+pmu {
+ compatible = "snps,archs-pct";
+};