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authorVinod Koul <vinod.koul@intel.com>2017-02-21 18:44:27 +0300
committerVinod Koul <vinod.koul@intel.com>2017-02-21 18:44:27 +0300
commit8a3ec58382bfb5e9c6b63f47e1bd6335aafc980e (patch)
treebeadc3259fdd1461af903bcf4d1fe4873fed1144 /Documentation
parent25036f2a7377d7135ce9848d58d14b5bc061541d (diff)
parent5df4eb453cbdad34ea55c0ce984a376b33442aa1 (diff)
downloadlinux-8a3ec58382bfb5e9c6b63f47e1bd6335aafc980e.tar.xz
Merge branch 'topic/stm32-dma' into for-linus
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/dma/stm32-dma.txt5
1 files changed, 2 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/dma/stm32-dma.txt b/Documentation/devicetree/bindings/dma/stm32-dma.txt
index 70cd13f1588a..4408af693d0c 100644
--- a/Documentation/devicetree/bindings/dma/stm32-dma.txt
+++ b/Documentation/devicetree/bindings/dma/stm32-dma.txt
@@ -40,8 +40,7 @@ Example:
DMA clients connected to the STM32 DMA controller must use the format
described in the dma.txt file, using a five-cell specifier for each
-channel: a phandle plus four integer cells.
-The four cells in order are:
+channel: a phandle to the DMA controller plus the following four integer cells:
1. The channel id
2. The request line number
@@ -61,7 +60,7 @@ The four cells in order are:
0x1: medium
0x2: high
0x3: very high
-5. A 32bit mask specifying the DMA FIFO threshold configuration which are device
+4. A 32bit mask specifying the DMA FIFO threshold configuration which are device
dependent:
-bit 0-1: Fifo threshold
0x0: 1/4 full FIFO