Merge tag 'drm-msm-next-2018-03-20' of git://people.freedesktop.org/~robclark/linux into drm-next

Updates for 4.17.  Sorry, running a bit late on this, didn't have a
chance to send pull-req before heading to linaro.  But it has all been
in linux-next for a while.  Main updates:

 + DSI updates from 10nm / SDM845
 + fix for race condition with a3xx/a4xx fence completion irq
 + some refactoring/prep work for eventual a6xx support (ie. when we have
   a userspace)
 + a5xx debugfs enhancements
 + some mdp5 fixes/cleanups to prepare for eventually merging writeback
   support (ie. when we have a userspace)

* tag 'drm-msm-next-2018-03-20' of git://people.freedesktop.org/~robclark/linux: (36 commits)
  drm/msm: fix building without debugfs
  drm/msm/mdp5: don't pre-reserve LM's if no dual-dsi
  drm/msm/mdp5: add missing LM flush bits
  drm/msm/mdp5: print a bit more of the atomic state
  drm/msm/mdp5: rework CTL START signal handling
  drm/msm: Trigger fence completion from GPU
  drm/msm/dsi: fix direct caller of msm_gem_free_object()
  drm/msm: strip out msm_fence_cb
  drm/msm: rename mdp->disp
  drm/msm/dsi: Fix potential NULL pointer dereference in msm_dsi_modeset_init
  drm/msm/adreno/a5xx_debugfs: fix potential NULL pointer dereference
  drm/msm/dsi: Get byte_intf_clk only for versions that need it
  drm/msm/adreno: Use generic function to load firmware to a buffer object
  drm/msm/adreno: Define a list of firmware files to load per target
  drm/msm/adreno: Rename gpmufw to powerfw
  drm/msm: Pass the correct aperture end to drm_mm_init
  drm/msm/gpu: Set number of clocks to 0 if the list allocation fails
  drm/msm: Replace gem_object deprecated functions
  drm/msm/hdmi: fix semicolon.cocci warnings
  drm/msm/mdp5: Fix trailing semicolon
  ...

1 files changed, 20 insertions, 6 deletions

diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt
index a6671bd2c85a..518e9cdf0d4b 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi.txt
+++ b/Documentation/devicetree/bindings/display/msm/dsi.txt
@@ -7,8 +7,6 @@ Required properties:
 - reg: Physical base address and length of the registers of controller
 - reg-names: The names of register regions. The following regions are required:
   * "dsi_ctrl"
-- qcom,dsi-host-index: The ID of DSI controller hardware instance. This should
-  be 0 or 1, since we have 2 DSI controllers at most for now.
 - interrupts: The interrupt signal from the DSI block.
 - power-domains: Should be <&mmcc MDSS_GDSC>.
 - clocks: Phandles to device clocks.
@@ -22,6 +20,8 @@ Required properties:
   * "core"
   For DSIv2, we need an additional clock:
    * "src"
+  For DSI6G v2.0 onwards, we need also need the clock:
+   * "byte_intf"
 - assigned-clocks: Parents of "byte" and "pixel" for the given platform.
 - assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
   by a DSI PHY block. See [1] for details on clock bindings.
@@ -88,21 +88,35 @@ Required properties:
   * "qcom,dsi-phy-28nm-lp"
   * "qcom,dsi-phy-20nm"
   * "qcom,dsi-phy-28nm-8960"
-- reg: Physical base address and length of the registers of PLL, PHY and PHY
-  regulator
+  * "qcom,dsi-phy-14nm"
+  * "qcom,dsi-phy-10nm"
+- reg: Physical base address and length of the registers of PLL, PHY. Some
+  revisions require the PHY regulator base address, whereas others require the
+  PHY lane base address. See below for each PHY revision.
 - reg-names: The names of register regions. The following regions are required:
+  For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
   * "dsi_pll"
   * "dsi_phy"
   * "dsi_phy_regulator"
+  For DSI 14nm and 10nm PHYs:
+  * "dsi_pll"
+  * "dsi_phy"
+  * "dsi_phy_lane"
 - clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
   2 clocks: A byte clock (index 0), and a pixel clock (index 1).
-- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should
-  be 0 or 1, since we have 2 DSI PHYs at most for now.
 - power-domains: Should be <&mmcc MDSS_GDSC>.
 - clocks: Phandles to device clocks. See [1] for details on clock bindings.
 - clock-names: the following clocks are required:
   * "iface"
+  For 28nm HPM/LP, 28nm 8960 PHYs:
+- vddio-supply: phandle to vdd-io regulator device node
+  For 20nm PHY:
 - vddio-supply: phandle to vdd-io regulator device node
+- vcca-supply: phandle to vcca regulator device node
+  For 14nm PHY:
+- vcca-supply: phandle to vcca regulator device node
+  For 10nm PHY:
+- vdds-supply: phandle to vdds regulator device node
 
 Optional properties:
 - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY