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authorRobert Jarzmik <robert.jarzmik@free.fr>2016-10-17 22:45:32 +0300
committerDavid S. Miller <davem@davemloft.net>2016-10-18 21:14:21 +0300
commitc4055a8cf7ba0042947309d1eada4d842bd3d8b7 (patch)
tree3cd14a3eabd49dbdbc4684043985dbb22bf2337a /Documentation
parent9c365f31775c43462e431bf5ff3c569190a1a08f (diff)
downloadlinux-c4055a8cf7ba0042947309d1eada4d842bd3d8b7.tar.xz
net: smsc91x: add u16 workaround for pxa platforms
Add a workaround for mainstone, idp and stargate2 boards, for u16 writes which must be aligned on 32 bits addresses. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Cc: Jeremy Linton <jeremy.linton@arm.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/net/smsc-lan91c111.txt2
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/net/smsc-lan91c111.txt b/Documentation/devicetree/bindings/net/smsc-lan91c111.txt
index e77e167593db..309e37eb7c7c 100644
--- a/Documentation/devicetree/bindings/net/smsc-lan91c111.txt
+++ b/Documentation/devicetree/bindings/net/smsc-lan91c111.txt
@@ -13,3 +13,5 @@ Optional properties:
16-bit access only.
- power-gpios: GPIO to control the PWRDWN pin
- reset-gpios: GPIO to control the RESET pin
+- pxa-u16-align4 : Boolean, put in place the workaround the force all
+ u16 writes to be 32 bits aligned