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authorLinus Torvalds <torvalds@linux-foundation.org>2016-10-05 21:37:14 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2016-10-05 21:37:14 +0300
commitd268dbe76a53d72cc41316eb59e7968db60e77ad (patch)
treec79635239b3e7c7decdb883efd64cb315a184af5 /Documentation
parent64cbd16a8751fde075aa103dc7823a8c05805104 (diff)
parent6bcf3f63394b9c4f133e4499349d786d7f531473 (diff)
downloadlinux-d268dbe76a53d72cc41316eb59e7968db60e77ad.tar.xz
Merge tag 'pinctrl-v4.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.9 cycle. General improvements: - nicer debugfs output with one pin/config pair per line. - continued efforts to strictify module vs bool. - constification and similar from Coccinelle engineers. - return error from pinctrl_bind_pins() - pulling in the ability to selectively disable mapping of unusable IRQs from the GPIO subsystem. New drivers: - new driver for the Aspeed pin controller family: AST2400 (G4) and AST2500 (G5) are supported. These are used by OpenBMC on the IBM Witherspoon platform. - new subdriver for the Allwinner sunxi GR8. Driver improvements: - drop default IRQ trigger types assigned during IRQ mapping on AT91 and Nomadik. This error was identified by improvements in the IRQ core by Marc Zyngier. - active high/low types on the GPIO IRQs for the ST pin controller. - IRQ support on GPIOs on the STM32 pin controller. - Renesas Super-H/ARM sh-pfc: continued massive developments. - misc MXC improvements. - SPDIF on the Allwiner A31 SoC - IR remote and SPI NOR flash, NAND flash, I2C pins on the AMLogic SoC. - PWM pins on the Meson. - do not map unusable IRQs (taken by BIOS) on the Intel Cherryview. - add GPIO IRQ wakeup support to the Intel driver so we can wake up from button pushes. Deprecation: - delete the obsolete STiH415/6 SoC support" * tag 'pinctrl-v4.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (75 commits) pinctrl: qcom: fix masking of pinmux functions pinctrl: intel: Configure GPIO chip IRQ as wakeup interrupts pinctrl: cherryview: Convert to use devm_gpiochip_add_data() pinctrl: cherryview: Do not add all southwest and north GPIOs to IRQ domain gpiolib: Make it possible to exclude GPIOs from IRQ domain pinctrl: nomadik: don't default-flag IRQs as falling pinctrl: st: Remove obsolete platforms from pinctrl-st dt doc pinctrl: st: Remove STiH415/6 SoC pinctrl driver support. pinctrl: amlogic: gxbb: add i2c pins pinctrl: amlogic: gxbb: add nand pins pinctrl: stm32: add IRQ_DOMAIN_HIERARCHY dependency pinctrl: amlogic: gxbb: add spi nor pins pinctrl: sh-pfc: r8a7794: Implement voltage switching for SDHI pinctrl: sh-pfc: r8a7791: Implement voltage switching for SDHI pinctrl: sh-pfc: Add PORT_GP_24 helper macro pinctrl: Fix "st,syscfg" definition for STM32 pinctrl driver: base: pinctrl: return error from pinctrl_bind_pins() pinctrl: meson-gxbb: add the missing SDIO interrupt pin pinctrl: aspeed: fix regmap error handling pinctrl: mediatek: constify gpio_chip structures ...
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt1
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt65
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt39
-rw-r--r--Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt5
-rw-r--r--Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt5
-rw-r--r--Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt2
-rw-r--r--Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt5
-rw-r--r--Documentation/gpio/driver.txt6
8 files changed, 108 insertions, 20 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 69617220c5d6..1685821eea41 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -23,6 +23,7 @@ Required properties:
"allwinner,sun8i-h3-pinctrl"
"allwinner,sun8i-h3-r-pinctrl"
"allwinner,sun50i-a64-pinctrl"
+ "nextthing,gr8-pinctrl"
- reg: Should contain the register physical address and length for the
pin controller.
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
new file mode 100644
index 000000000000..5e60ad18f147
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
@@ -0,0 +1,65 @@
+Aspeed Pin Controllers
+----------------------
+
+The Aspeed SoCs vary in functionality inside a generation but have a common mux
+device register layout.
+
+Required properties:
+- compatible : Should be any one of the following:
+ "aspeed,ast2400-pinctrl"
+ "aspeed,g4-pinctrl"
+ "aspeed,ast2500-pinctrl"
+ "aspeed,g5-pinctrl"
+
+The pin controller node should be a child of a syscon node with the required
+property:
+- compatible: "syscon", "simple-mfd"
+
+Refer to the the bindings described in
+Documentation/devicetree/bindings/mfd/syscon.txt
+
+Subnode Format
+--------------
+
+The required properties of child nodes are (as defined in pinctrl-bindings):
+- function
+- groups
+
+Each function has only one associated pin group. Each group is named by its
+function. The following values for the function and groups properties are
+supported:
+
+aspeed,ast2400-pinctrl, aspeed,g4-pinctrl:
+
+ACPI BMCINT DDCCLK DDCDAT FLACK FLBUSY FLWP GPID0 GPIE0 GPIE2 GPIE4 GPIE6 I2C10
+I2C11 I2C12 I2C13 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8 I2C9 LPCPD LPCPME LPCSMI MDIO1
+MDIO2 NCTS1 NCTS3 NCTS4 NDCD1 NDCD3 NDCD4 NDSR1 NDSR3 NDTR1 NDTR3 NRI1 NRI3
+NRI4 NRTS1 NRTS3 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RMII1 ROM16
+ROM8 ROMCS1 ROMCS2 ROMCS3 ROMCS4 RXD1 RXD3 RXD4 SD1 SGPMI SIOPBI SIOPBO TIMER3
+TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD3 TXD4 UART6 VGAHS VGAVS VPI18 VPI24 VPI30
+VPO12 VPO24
+
+aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
+
+GPID0 GPID2 GPIE0 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8
+I2C9 MAC1LINK MDIO1 MDIO2 OSCCLK PEWAKE PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7
+RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8
+
+Examples:
+
+syscon: scu@1e6e2000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x1e6e2000 0x1a8>;
+
+ pinctrl: pinctrl {
+ compatible = "aspeed,g4-pinctrl";
+
+ pinctrl_i2c3_default: i2c3_default {
+ function = "I2C3";
+ groups = "I2C3";
+ };
+ };
+};
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices.
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
index 26bcb18f4e60..013c675b5b64 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
@@ -30,8 +30,7 @@ Second type has a dedicated interrupt per gpio bank.
Pin controller node:
Required properties:
-- compatible : should be "st,<SOC>-<pio-block>-pinctrl"
- like st,stih415-sbc-pinctrl, st,stih415-front-pinctrl and so on.
+- compatible : should be "st,stih407-<pio-block>-pinctrl"
- st,syscfg : Should be a phandle of the syscfg node.
- st,retime-pin-mask : Should be mask to specify which pins can be retimed.
If the property is not present, it is assumed that all the pins in the
@@ -50,7 +49,11 @@ Optional properties:
GPIO controller/bank node.
Required properties:
- gpio-controller : Indicates this device is a GPIO controller
-- #gpio-cells : Should be one. The first cell is the pin number.
+- #gpio-cells : Must be two.
+ - First cell: specifies the pin number inside the controller
+ - Second cell: specifies whether the pin is logically inverted.
+ - 0 = active high
+ - 1 = active low
- st,bank-name : Should be a name string for this bank as specified in
datasheet.
@@ -76,23 +79,23 @@ include/dt-bindings/interrupt-controller/irq.h
Example:
pin-controller-sbc {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,stih415-sbc-pinctrl";
- st,syscfg = <&syscfg_sbc>;
- reg = <0xfe61f080 0x4>;
- reg-names = "irqmux";
- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irqmux";
- ranges = <0 0xfe610000 0x5000>;
-
- PIO0: gpio@fe610000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stih407-sbc-pinctrl";
+ st,syscfg = <&syscfg_sbc>;
+ reg = <0x0961f080 0x4>;
+ reg-names = "irqmux";
+ interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
+ interrupt-names = "irqmux";
+ ranges = <0 0x09610000 0x6000>;
+
+ pio0: gpio@09610000 {
gpio-controller;
- #gpio-cells = <1>;
+ #gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- reg = <0 0x100>;
- st,bank-name = "PIO0";
+ reg = <0x0 0x100>;
+ st,bank-name = "PIO0";
};
...
pin-functions nodes follow...
@@ -162,7 +165,7 @@ pin-controller {
sdhci0:sdhci@fe810000{
...
- interrupt-parent = <&PIO3>;
+ interrupt-parent = <&pio3>;
#interrupt-cells = <2>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; /* Interrupt line via PIO3-3 */
interrupt-names = "card-detect";
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
index a54c39ebbf8b..8d893a874634 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
@@ -17,6 +17,9 @@ PMIC's from Qualcomm.
"qcom,pm8994-gpio"
"qcom,pma8084-gpio"
+ And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio"
+ if the device is on an spmi bus or an ssbi bus respectively
+
- reg:
Usage: required
Value type: <prop-encoded-array>
@@ -183,7 +186,7 @@ to specify in a pin configuration subnode:
Example:
pm8921_gpio: gpio@150 {
- compatible = "qcom,pm8921-gpio";
+ compatible = "qcom,pm8921-gpio", "qcom,ssbi-gpio";
reg = <0x150 0x160>;
interrupts = <192 1>, <193 1>, <194 1>,
<195 1>, <196 1>, <197 1>,
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt
index b484ba1af78c..2ab95bc26066 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt
@@ -19,6 +19,9 @@ of PMIC's from Qualcomm.
"qcom,pm8994-mpp",
"qcom,pma8084-mpp",
+ And must contain either "qcom,spmi-mpp" or "qcom,ssbi-mpp"
+ if the device is on an spmi bus or an ssbi bus respectively.
+
- reg:
Usage: required
Value type: <prop-encoded-array>
@@ -158,7 +161,7 @@ to specify in a pin configuration subnode:
Example:
mpps@a000 {
- compatible = "qcom,pm8841-mpp";
+ compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp";
reg = <0xa000>;
gpio-controller;
#gpio-cells = <2>;
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
index e4cf022c992e..13df9498311a 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -17,9 +17,11 @@ Required Properties:
- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
- "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
- "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.
+ - "renesas,pfc-r8a7792": for R8A7792 (R-Car V2H) compatible pin-controller.
- "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller.
- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
- "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
+ - "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller.
- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
- reg: Base address and length of each memory resource used by the pin
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
index 587bffb9cbc6..f9753c416974 100644
--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
@@ -14,6 +14,11 @@ Required properies:
- #size-cells : The value of this property must be 1
- ranges : defines mapping between pin controller node (parent) to
gpio-bank node (children).
+ - interrupt-parent: phandle of the interrupt parent to which the external
+ GPIO interrupts are forwarded to.
+ - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node
+ which includes IRQ mux selection register, and the offset of the IRQ mux
+ selection register.
- pins-are-numbered: Specify the subnodes are using numbered pinmux to
specify pins.
diff --git a/Documentation/gpio/driver.txt b/Documentation/gpio/driver.txt
index 6cb35a78eff4..368d5a294d89 100644
--- a/Documentation/gpio/driver.txt
+++ b/Documentation/gpio/driver.txt
@@ -262,6 +262,12 @@ symbol:
to the container using container_of().
(See Documentation/driver-model/design-patterns.txt)
+ If there is a need to exclude certain GPIOs from the IRQ domain, one can
+ set .irq_need_valid_mask of the gpiochip before gpiochip_add_data() is
+ called. This allocates .irq_valid_mask with as many bits set as there are
+ GPIOs in the chip. Drivers can exclude GPIOs by clearing bits from this
+ mask. The mask must be filled in before gpiochip_irqchip_add() is called.
+
* gpiochip_set_chained_irqchip(): sets up a chained irq handler for a
gpio_chip from a parent IRQ and passes the struct gpio_chip* as handler
data. (Notice handler data, since the irqchip data is likely used by the