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authorLinus Torvalds <torvalds@linux-foundation.org>2014-04-02 00:10:49 +0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-04-02 00:10:49 +0400
commitd64b3932531cbc0c9d6bdb744446934435e9d6af (patch)
tree32220446dde284e82f26616b852fa51fd8d0111d /Documentation
parent4dedde7c7a18f55180574f934dbc1be84ca0400b (diff)
parent43f23a0660fa0fdc74c7b1bfc5a209883dbf8153 (diff)
downloadlinux-d64b3932531cbc0c9d6bdb744446934435e9d6af.tar.xz
Merge tag 'pinctrl-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control bulk changes from Linus Walleij: "Pin control bulk changes for the v3.15 series, no new core functionality this time, just incremental driver updates: - A large refactoring of the MVEBU (Marvell) driver. - A large refactoring of the Tegra (nVidia) driver. - GPIO interrupt including soft edges support in the STi driver. - Misc updates to PFC (Renesas), AT91, ADI2 (Blackfin), pinctrl-single, sirf (CSR), msm (Qualcomm), Exynos (Samsung), sunxi (AllWinner), i.MX (Freescale), Baytrail" * tag 'pinctrl-v3.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits) pinctrl: tegra: add some missing Tegra114 entries pinctrl: tegra: fix some mistakes in Tegra124 pinctrl: msm: fix up out-of-order merge conflict pinctrl: st: Fix error check for of_irq_to_resource usage pinctrl: tegra: consistency cleanup pinctrl: tegra: dynamically calculate function list of groups pinctrl: tegra: init Tegra20/30 at module_init time pinctrl: st: Use ARRAY_SIZE instead of raw value for number of delays pinctrl: st: add pinctrl support for the STiH407 SoC pinctrl: st: Enhance the controller to manage unavailable registers pinctrl: msm: Simplify msm_config_reg() and callers pinctrl: msm: Remove impossible WARN_ON()s pinctrl: msm: Replace lookup tables with math pinctrl: msm: Drop OF_IRQ dependency pinctrl: msm: Drop unused includes pinctrl: msm: Check for ngpios > MAX_NR_GPIO pinctrl: msm: Silence recursive lockdep warning pinctrl: mvebu: silence WARN to dev_warn pinctrl: msm: drop wake_irqs bitmap pinctrl-baytrail: add function mux checking in gpio pin request ...
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/arm/marvell,dove.txt22
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt1
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt82
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt80
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt1
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt1
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt1
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt2
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt7
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt73
-rw-r--r--Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt14
-rw-r--r--Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt1
12 files changed, 271 insertions, 14 deletions
diff --git a/Documentation/devicetree/bindings/arm/marvell,dove.txt b/Documentation/devicetree/bindings/arm/marvell,dove.txt
new file mode 100644
index 000000000000..aaaf64c56e44
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell,dove.txt
@@ -0,0 +1,22 @@
+Marvell Dove Platforms Device Tree Bindings
+-----------------------------------------------
+
+Boards with a Marvell Dove SoC shall have the following properties:
+
+Required root node property:
+- compatible: must contain "marvell,dove";
+
+* Global Configuration registers
+
+Global Configuration registers of Dove SoC are shared by a syscon node.
+
+Required properties:
+- compatible: must contain "marvell,dove-global-config" and "syscon".
+- reg: base address and size of the Global Configuration registers.
+
+Example:
+
+gconf: global-config@e802c {
+ compatible = "marvell,dove-global-config", "syscon";
+ reg = <0xe802c 0x14>;
+};
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
index 01ef408e205f..adda2a8d1d52 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
@@ -5,6 +5,7 @@ part and usage.
Required properties:
- compatible: "marvell,88f6710-pinctrl"
+- reg: register specifier of MPP registers
Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt
new file mode 100644
index 000000000000..7de0cda4a379
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt
@@ -0,0 +1,82 @@
+* Marvell Armada 375 SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6720-pinctrl"
+- reg: register specifier of MPP registers
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name pins functions
+================================================================================
+mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1)
+mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi)
+mpp2 2 gpio, dev(ad4), ptp(eventreq), led(c0), audio(sdi)
+mpp3 3 gpio, dev(ad5), ptp(triggen), led(p3), audio(mclk)
+mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso)
+mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2)
+mpp6 6 gpio, dev(ad0), led(p1), audio(rclk)
+mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk)
+mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0)
+mpp9 9 gpio, nf(wen), spi0(sck), spi1(sck)
+mpp10 10 gpio, nf(ren), dram(vttctrl), led(c1)
+mpp11 11 gpio, dev(a0), led(c2), audio(sdo)
+mpp12 12 gpio, dev(a1), audio(bclk)
+mpp13 13 gpio, dev(readyn), pcie0(rstoutn), pcie1(rstoutn)
+mpp14 14 gpio, i2c0(sda), uart1(txd)
+mpp15 15 gpio, i2c0(sck), uart1(rxd)
+mpp16 16 gpio, uart0(txd)
+mpp17 17 gpio, uart0(rxd)
+mpp18 18 gpio, tdm(intn)
+mpp19 19 gpio, tdm(rstn)
+mpp20 20 gpio, tdm(pclk)
+mpp21 21 gpio, tdm(fsync)
+mpp22 22 gpio, tdm(drx)
+mpp23 23 gpio, tdm(dtx)
+mpp24 24 gpio, led(p0), ge1(rxd0), sd(cmd), uart0(rts)
+mpp25 25 gpio, led(p2), ge1(rxd1), sd(d0), uart0(cts)
+mpp26 26 gpio, pcie0(clkreq), ge1(rxd2), sd(d2), uart1(rts)
+mpp27 27 gpio, pcie1(clkreq), ge1(rxd3), sd(d1), uart1(cts)
+mpp28 28 gpio, led(p3), ge1(txctl), sd(clk)
+mpp29 29 gpio, pcie1(clkreq), ge1(rxclk), sd(d3)
+mpp30 30 gpio, ge1(txd0), spi1(cs0)
+mpp31 31 gpio, ge1(txd1), spi1(mosi)
+mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(triggen)
+mpp33 33 gpio, ge1(txd3), spi1(miso)
+mpp34 34 gpio, ge1(txclkout), spi1(sck)
+mpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2)
+mpp36 36 gpio, pcie0(clkreq)
+mpp37 37 gpio, pcie0(clkreq), tdm(intn), ge(mdc)
+mpp38 38 gpio, pcie1(clkreq), ge(mdio)
+mpp39 39 gpio, ref(clkout)
+mpp40 40 gpio, uart1(txd)
+mpp41 41 gpio, uart1(rxd)
+mpp42 42 gpio, spi1(cs2), led(c0)
+mpp43 43 gpio, sata0(prsnt), dram(vttctrl)
+mpp44 44 gpio, sata0(prsnt)
+mpp45 45 gpio, spi0(cs2), pcie0(rstoutn)
+mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0)
+mpp47 47 gpio, led(p1), ge0(txd1), ge1(txd1)
+mpp48 48 gpio, led(p2), ge0(txd2), ge1(txd2)
+mpp49 49 gpio, led(p3), ge0(txd3), ge1(txd3)
+mpp50 50 gpio, led(c0), ge0(rxd0), ge1(rxd0)
+mpp51 51 gpio, led(c1), ge0(rxd1), ge1(rxd1)
+mpp52 52 gpio, led(c2), ge0(rxd2), ge1(rxd2)
+mpp53 53 gpio, pcie1(rstoutn), ge0(rxd3), ge1(rxd3)
+mpp54 54 gpio, pcie0(rstoutn), ge0(rxctl), ge1(rxctl)
+mpp55 55 gpio, ge0(rxclk), ge1(rxclk)
+mpp56 56 gpio, ge0(txclkout), ge1(txclkout)
+mpp57 57 gpio, ge0(txctl), ge1(txctl)
+mpp58 58 gpio, led(c0)
+mpp59 59 gpio, led(c1)
+mpp60 60 gpio, uart1(txd), led(c2)
+mpp61 61 gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0)
+mpp62 62 gpio, i2c1(sck), led(p1)
+mpp63 63 gpio, ptp(triggen), led(p2)
+mpp64 64 gpio, dram(vttctrl), led(p3)
+mpp65 65 gpio, sata1(prsnt)
+mpp66 66 gpio, ptp(eventreq), spi1(cs3)
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt
new file mode 100644
index 000000000000..b17c96849fc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt
@@ -0,0 +1,80 @@
+* Marvell Armada 380/385 SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6810-pinctrl", "marvell,88f6820-pinctrl" or
+ "marvell,88f6828-pinctrl" depending on the specific variant of the
+ SoC being used.
+- reg: register specifier of MPP registers
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name pins functions
+================================================================================
+mpp0 0 gpio, ua0(rxd)
+mpp1 1 gpio, ua0(txd)
+mpp2 2 gpio, i2c0(sck)
+mpp3 3 gpio, i2c0(sda)
+mpp4 4 gpio, ge(mdc), ua1(txd), ua0(rts)
+mpp5 5 gpio, ge(mdio), ua1(rxd), ua0(cts)
+mpp6 6 gpio, ge0(txclkout), ge0(crs), dev(cs3)
+mpp7 7 gpio, ge0(txd0), dev(ad9)
+mpp8 8 gpio, ge0(txd1), dev(ad10)
+mpp9 9 gpio, ge0(txd2), dev(ad11)
+mpp10 10 gpio, ge0(txd3), dev(ad12)
+mpp11 11 gpio, ge0(txctl), dev(ad13)
+mpp12 12 gpio, ge0(rxd0), pcie0(rstout), pcie1(rstout) [1], spi0(cs1), dev(ad14)
+mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15)
+mpp14 14 gpio, ge0(rxd2), ptp(clk), m(vtt_ctrl), spi0(cs3), dev(wen1)
+mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi), pcie1(rstout) [1]
+mpp16 16 gpio, ge0(rxctl), ge(mdio slave), m(decc_err), spi0(miso), pcie0(clkreq)
+mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt)
+mpp18 18 gpio, ge0(rxerr), ptp(trig_gen), ua1(txd), spi0(cs0), pcie1(rstout) [1]
+mpp19 19 gpio, ge0(col), ptp(event_req), pcie0(clkreq), sata1(prsnt), ua0(cts)
+mpp20 20 gpio, ge0(txclk), ptp(clk), pcie1(rstout) [1], sata0(prsnt), ua0(rts)
+mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs)
+mpp22 22 gpio, spi0(mosi), dev(ad0)
+mpp23 23 gpio, spi0(sck), dev(ad2)
+mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready)
+mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0)
+mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1)
+mpp27 27 gpio, spi0(cs3), ge1(txclkout), i2c1(sda), sd0(d7), dev(cs2)
+mpp28 28 gpio, ge1(txd0), sd0(clk), dev(ad5)
+mpp29 29 gpio, ge1(txd1), dev(ale0)
+mpp30 30 gpio, ge1(txd2), dev(oen)
+mpp31 31 gpio, ge1(txd3), dev(ale1)
+mpp32 32 gpio, ge1(txctl), dev(wen0)
+mpp33 33 gpio, m(decc_err), dev(ad3)
+mpp34 34 gpio, dev(ad1)
+mpp35 35 gpio, ref(clk_out1), dev(a1)
+mpp36 36 gpio, ptp(trig_gen), dev(a0)
+mpp37 37 gpio, ptp(clk), ge1(rxclk), sd0(d3), dev(ad8)
+mpp38 38 gpio, ptp(event_req), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4)
+mpp39 39 gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2)
+mpp40 40 gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6)
+mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last)
+mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7)
+mpp43 43 gpio, pcie0(clkreq), m(vtt_ctrl), m(decc_err), pcie0(rstout), dev(clkout)
+mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3], pcie0(rstout)
+mpp45 45 gpio, ref(clk_out0), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout)
+mpp46 46 gpio, ref(clk_out1), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout)
+mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], spi1(cs2), sata3(prsnt) [2]
+mpp48 48 gpio, sata0(prsnt), m(vtt_ctrl), tdm2c(pclk), audio(mclk), sd0(d4)
+mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm2c(fsync), audio(lrclk), sd0(d5)
+mpp50 50 gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(drx), audio(extclk), sd0(cmd)
+mpp51 51 gpio, tdm2c(dtx), audio(sdo), m(decc_err)
+mpp52 52 gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(intn), audio(sdi), sd0(d6)
+mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm2c(rstn), audio(bclk), sd0(d7)
+mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), pcie1(rstout) [1], sd0(d3)
+mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0)
+mpp56 56 gpio, ua1(rts), ge(mdc), m(decc_err), spi1(mosi)
+mpp57 57 gpio, spi1(sck), sd0(clk)
+mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1)
+mpp59 59 gpio, pcie0(rstout), i2c1(sda), pcie1(rstout) [1], spi1(cs0), sd0(d2)
+
+[1]: only available on 88F6820 and 88F6828
+[2]: only available on 88F6828
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
index bfa0a2e5e0cb..373dbccd7ab0 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
@@ -6,6 +6,7 @@ part and usage.
Required properties:
- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
"marvell,mv78460-pinctrl"
+- reg: register specifier of MPP registers
This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
index 50ec3512a292..cf52477cc7ee 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
@@ -6,6 +6,7 @@ part and usage.
Required properties:
- compatible: "marvell,dove-pinctrl"
- clocks: (optional) phandle of pdma clock
+- reg: register specifiers of MPP, MPP4, and PMU MPP registers
Available mpp pins/groups and functions:
Note: brackets (x) are not part of the mpp name for marvell,function and given
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
index 95daf6335c37..730444a9a4de 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
@@ -8,6 +8,7 @@ Required properties:
"marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
"marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
"marvell,98dx4122-pinctrl"
+- reg: register specifier of MPP registers
This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
index 0a26c3aa4e6d..0c09f4eb2af0 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
@@ -37,7 +37,7 @@ uart1: serial@12100 {
pinctrl: pinctrl@d0200 {
compatible = "marvell,dove-pinctrl";
- reg = <0xd0200 0x20>;
+ reg = <0xd0200 0x14>, <0xd0440 0x04>, <0xd802c 0x08>;
pmx_uart1_sw: pmx-uart1-sw {
marvell,pins = "mpp_uart1";
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
index bc0dfdfdb148..66dcaa9efd74 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
@@ -63,6 +63,13 @@ Optional properties:
/* input, enable bits, disable bits, mask */
pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;
+- pinctrl-single,low-power-mode : array of value that are used to configure
+ low power mode of this pin. For some silicons, the low power mode will
+ control the output of the pin when the pad including the pin enter low
+ power mode.
+ /* low power mode value, mask */
+ pinctrl-single,low-power-mode = <0x288 0x388>;
+
- pinctrl-single,gpio-range : list of value that are used to configure a GPIO
range. They're value of subnode phandle, pin base in pinctrl device, pin
number in this range, GPIO function value of this GPIO range.
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
index 05bf82a07dfd..4bd5be0e5e7d 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
@@ -11,18 +11,68 @@ Pull Up (PU) are driven by the related PIO block.
ST pinctrl driver controls PIO multiplexing block and also interacts with
gpio driver to configure a pin.
-Required properties: (PIO multiplexing block)
+GPIO bank can have one of the two possible types of interrupt-wirings.
+
+First type is via irqmux, single interrupt is used by multiple gpio banks. This
+reduces number of overall interrupts numbers required. All these banks belong to
+a single pincontroller.
+ _________
+ | |----> [gpio-bank (n) ]
+ | |----> [gpio-bank (n + 1)]
+ [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
+ | |----> [gpio-bank (... )]
+ |_________|----> [gpio-bank (n + 7)]
+
+Second type has a dedicated interrupt per gpio bank.
+
+ [irqN]----> [gpio-bank (n)]
+
+
+Pin controller node:
+Required properties:
- compatible : should be "st,<SOC>-<pio-block>-pinctrl"
like st,stih415-sbc-pinctrl, st,stih415-front-pinctrl and so on.
-- gpio-controller : Indicates this device is a GPIO controller
-- #gpio-cells : Should be one. The first cell is the pin number.
+- st,syscfg : Should be a phandle of the syscfg node.
- st,retime-pin-mask : Should be mask to specify which pins can be retimed.
If the property is not present, it is assumed that all the pins in the
bank are capable of retiming. Retiming is mainly used to improve the
IO timing margins of external synchronous interfaces.
-- st,bank-name : Should be a name string for this bank as
- specified in datasheet.
-- st,syscfg : Should be a phandle of the syscfg node.
+- ranges : defines mapping between pin controller node (parent) to gpio-bank
+ node (children).
+
+Optional properties:
+- interrupts : Interrupt number of the irqmux. If the interrupt is shared
+ with other gpio banks via irqmux.
+ a irqline and gpio banks.
+- reg : irqmux memory resource. If irqmux is present.
+- reg-names : irqmux resource should be named as "irqmux".
+
+GPIO controller/bank node.
+Required properties:
+- gpio-controller : Indicates this device is a GPIO controller
+- #gpio-cells : Should be one. The first cell is the pin number.
+- st,bank-name : Should be a name string for this bank as specified in
+ datasheet.
+
+Optional properties:
+- interrupts : Interrupt number for this gpio bank. If there is a dedicated
+ interrupt wired up for this gpio bank.
+
+- interrupt-controller : Indicates this device is a interrupt controller. GPIO
+ bank can be an interrupt controller iff one of the interrupt type either via
+irqmux or a dedicated interrupt per bank is specified.
+
+- #interrupt-cells: the value of this property should be 2.
+ - First Cell: represents the external gpio interrupt number local to the
+ gpio interrupt space of the controller.
+ - Second Cell: flags to identify the type of the interrupt
+ - 1 = rising edge triggered
+ - 2 = falling edge triggered
+ - 3 = rising and falling edge triggered
+ - 4 = high level triggered
+ - 8 = low level triggered
+for related macros look in:
+include/dt-bindings/interrupt-controller/irq.h
Example:
pin-controller-sbc {
@@ -30,10 +80,17 @@ Example:
#size-cells = <1>;
compatible = "st,stih415-sbc-pinctrl";
st,syscfg = <&syscfg_sbc>;
+ reg = <0xfe61f080 0x4>;
+ reg-names = "irqmux";
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-names = "irqmux";
ranges = <0 0xfe610000 0x5000>;
+
PIO0: gpio@fe610000 {
gpio-controller;
#gpio-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
reg = <0 0x100>;
st,bank-name = "PIO0";
};
@@ -105,6 +162,10 @@ pin-controller {
sdhci0:sdhci@fe810000{
...
+ interrupt-parent = <&PIO3>;
+ #interrupt-cells = <2>;
+ interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; /* Interrupt line via PIO3-3 */
+ interrupts-names = "card-detect";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc>;
};
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt
index 4c352be5dd61..9fb89e3f61ea 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt
@@ -1,7 +1,7 @@
Qualcomm MSM8974 TLMM block
Required properties:
-- compatible: "qcom,msm8x74-pinctrl"
+- compatible: "qcom,msm8974-pinctrl"
- reg: Should be the base address and length of the TLMM block.
- interrupts: Should be the parent IRQ of the TLMM block.
- interrupt-controller: Marks the device node as an interrupt controller.
@@ -42,14 +42,14 @@ Non-empty subnodes must specify the 'pins' property.
Note that not all properties are valid for all pins.
-Valid values for qcom,pins are:
+Valid values for pins are:
gpio0-gpio145
Supports mux, bias and drive-strength
sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data
Supports bias and drive-strength
-Valid values for qcom,function are:
+Valid values for function are:
blsp_i2c2, blsp_i2c6, blsp_i2c11, blsp_spi1, blsp_uart2, blsp_uart8, slimbus
(Note that this is not yet the complete list of functions)
@@ -73,18 +73,18 @@ Example:
uart2_default: uart2_default {
mux {
- qcom,pins = "gpio4", "gpio5";
- qcom,function = "blsp_uart2";
+ pins = "gpio4", "gpio5";
+ function = "blsp_uart2";
};
tx {
- qcom,pins = "gpio4";
+ pins = "gpio4";
drive-strength = <4>;
bias-disable;
};
rx {
- qcom,pins = "gpio5";
+ pins = "gpio5";
drive-strength = <2>;
bias-pull-up;
};
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index 257677de3e6b..2b32783ba821 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -16,6 +16,7 @@ Required Properties:
- "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
- "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
- "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
+ - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of