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authorRoman Li <roman.li@amd.com>2024-01-10 01:31:33 +0300
committerAlex Deucher <alexander.deucher@amd.com>2024-01-26 00:00:24 +0300
commit196107eb1e1557df25e1425bbfb53e0f7588b80a (patch)
treed7f8897c49ced6298e3133f273d1385aafa41104 /LICENSES
parent955406e6fd241b2936e7f033a03b2956922c8f32 (diff)
downloadlinux-196107eb1e1557df25e1425bbfb53e0f7588b80a.tar.xz
drm/amd/display: Add IPS checks before dcn register access
[Why] With IPS enabled a system hangs once PSR is active. PSR active triggers transition to IPS2 state. While in IPS2 an access to dcn registers results in hard hang. Existing check doesn't cover for PSR sequence. [How] Safeguard register access by disabling idle optimization in atomic commit and crtc scanout. It will be re-enabled on next vblank. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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