diff options
author | Tony Lindgren <tony@atomide.com> | 2020-03-04 18:25:30 +0300 |
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committer | Tony Lindgren <tony@atomide.com> | 2020-03-06 18:20:01 +0300 |
commit | 1e666cb36072b67670bd4ef3e6008323c264bcdc (patch) | |
tree | a6cac17cf448b331aedd0ea1d40b853f43ee0f7e /arch/arm/boot/dts/am33xx.dtsi | |
parent | 9c1562ea71feb0b5fd700770bb935922d21c438e (diff) | |
download | linux-1e666cb36072b67670bd4ef3e6008323c264bcdc.tar.xz |
ARM: dts: Configure interconnect target module for am3 tptc1
We can now probe devices with device tree only configuration using
ti-sysc interconnect target module driver. Let's configure the
module, but keep the legacy "ti,hwmods" peroperty to avoid new boot
time warnings. The legacy property will be removed in later patches
together with the legacy platform data.
Let's also correct the custom node name to use generic node name dma.
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/am33xx.dtsi')
-rw-r--r-- | arch/arm/boot/dts/am33xx.dtsi | 26 |
1 files changed, 21 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 63c34219fcf6..40ed8e1bfbe6 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -245,12 +245,28 @@ }; }; - edma_tptc1: tptc@49900000 { - compatible = "ti,edma3-tptc"; + target-module@49900000 { + compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "tptc1"; - reg = <0x49900000 0x100000>; - interrupts = <113>; - interrupt-names = "edma3_tcerrint"; + reg = <0x49900000 0x4>, + <0x49900010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; + ti,sysc-midle = <SYSC_IDLE_FORCE>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_SMART>; + clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49900000 0x100000>; + + edma_tptc1: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <113>; + interrupt-names = "edma3_tcerrint"; + }; }; edma_tptc2: tptc@49a00000 { |