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authorRussell King <rmk+kernel@armlinux.org.uk>2017-01-02 17:59:02 +0300
committerGregory CLEMENT <gregory.clement@free-electrons.com>2017-01-04 13:38:53 +0300
commit54f0ec0a3d4861a4ea7c8fce6f7ca1aeb0089375 (patch)
tree88107e8dde61a4d126ac7715fcef51805e65a4e5 /arch/arm/boot/dts/armada-388-clearfog.dts
parentd5bd63358595dc0171ec848bf1e7969d11ad8837 (diff)
downloadlinux-54f0ec0a3d4861a4ea7c8fce6f7ca1aeb0089375.tar.xz
ARM: dts: armada388-clearfog: move second PCIe port
Move the second PCIe port to the clearfog .dts file as this is only present on the pro models. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/armada-388-clearfog.dts')
-rw-r--r--arch/arm/boot/dts/armada-388-clearfog.dts51
1 files changed, 51 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts
index 6b916305b47f..2c4a8ad98c4f 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
@@ -54,6 +54,23 @@
compatible = "solidrun,clearfog-a1", "marvell,armada388",
"marvell,armada385", "marvell,armada380";
+ soc {
+ internal-regs {
+ usb3@f0000 {
+ /* CON2, nearest CPU, USB2 only. */
+ status = "okay";
+ };
+ };
+
+ pcie-controller {
+ pcie@3,0 {
+ /* Port 2, Lane 0. CON2, nearest CPU. */
+ reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ };
+ };
+ };
+
dsa@0 {
compatible = "marvell,dsa";
dsa,ethernet = <&eth1>;
@@ -119,6 +136,40 @@
};
};
+&expander0 {
+ /*
+ * PCA9655 GPIO expander:
+ * 0-CON3 CLKREQ#
+ * 1-CON3 PERST#
+ * 2-CON2 PERST#
+ * 3-CON3 W_DISABLE
+ * 4-CON2 CLKREQ#
+ * 5-USB3 overcurrent
+ * 6-USB3 power
+ * 7-CON2 W_DISABLE
+ * 8-JP4 P1
+ * 9-JP4 P4
+ * 10-JP4 P5
+ * 11-m.2 DEVSLP
+ * 12-SFP_LOS
+ * 13-SFP_TX_FAULT
+ * 14-SFP_TX_DISABLE
+ * 15-SFP_MOD_DEF0
+ */
+ pcie2_0_clkreq {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "pcie2.0-clkreq";
+ };
+ pcie2_0_w_disable {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "pcie2.0-w-disable";
+ };
+};
+
&pinctrl {
clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
marvell,pins = "mpp46";