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authorYan Markman <ymarkman@marvell.com>2016-10-16 00:22:32 +0300
committerGregory CLEMENT <gregory.clement@free-electrons.com>2017-10-26 18:41:26 +0300
commitcda80a82ac3e89309706c027ada6ab232be1d640 (patch)
tree15f22dc1162f04a8a6d48360d7b70d3755639e4a /arch/arm/boot/dts/armada-39x.dtsi
parent2bbbd96357ce76cc45ec722c00f654aa7b189112 (diff)
downloadlinux-cda80a82ac3e89309706c027ada6ab232be1d640.tar.xz
ARM: dts: mvebu: pl310-cache disable double-linefill
Under heavy system stress mvebu SoC using Cortex A9 sporadically encountered instability issues. The "double linefill" feature of L2 cache was identified as causing dependency between read and write which lead to the deadlock. Especially, it was the cause of deadlock seen under heavy PCIe traffic, as this dependency violates PCIE overtaking rule. Fixes: c8f5a878e554 ("ARM: mvebu: use DT properties to fine-tune the L2 configuration") Cc: stable@vger.kernel.org Signed-off-by: Yan Markman <ymarkman@marvell.com> Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Nadav Haklai <nadavh@marvell.com> [gregory.clement@free-electrons.com: reformulate commit log, add Armada 375 and add Fixes tag] Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/armada-39x.dtsi')
-rw-r--r--arch/arm/boot/dts/armada-39x.dtsi4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi
index ea657071e278..5218bd2a248d 100644
--- a/arch/arm/boot/dts/armada-39x.dtsi
+++ b/arch/arm/boot/dts/armada-39x.dtsi
@@ -111,9 +111,9 @@
reg = <0x8000 0x1000>;
cache-unified;
cache-level = <2>;
- arm,double-linefill-incr = <1>;
+ arm,double-linefill-incr = <0>;
arm,double-linefill-wrap = <0>;
- arm,double-linefill = <1>;
+ arm,double-linefill = <0>;
prefetch-data = <1>;
};