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authorJon Mason <jonmason@broadcom.com>2016-05-06 02:29:31 +0300
committerFlorian Fainelli <f.fainelli@gmail.com>2016-05-31 20:56:10 +0300
commitf7f20cba26b9ee8865156ca9df264510cfcebbf6 (patch)
treeb43e902bdb69d5226a6802e2e7a38ed912e34659 /arch/arm/boot/dts/bcm-nsp.dtsi
parentd71eb941208883404d44380807726afdc20ab98a (diff)
downloadlinux-f7f20cba26b9ee8865156ca9df264510cfcebbf6.tar.xz
ARM: dts: NSP: modify second CPU address
NSP B0 has a different address for the second core. Since there should not be any Ax versions in the field, it should be safe to universally change this. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Diffstat (limited to 'arch/arm/boot/dts/bcm-nsp.dtsi')
-rw-r--r--arch/arm/boot/dts/bcm-nsp.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index a44bf29fc5b6..1759e650d225 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -57,7 +57,7 @@
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
enable-method = "brcm,bcm-nsp-smp";
- secondary-boot-reg = <0xffff042c>;
+ secondary-boot-reg = <0xffff0fec>;
reg = <0x1>;
};
};