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authorSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>2014-10-30 13:21:27 +0300
committerSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>2014-11-12 02:17:12 +0300
commit878a3ee38d6e876093f742403316e91301303a3d (patch)
tree74fd20cc234da6b2019911c04e340c24c0e6b217 /arch/arm/boot/dts/berlin2.dtsi
parente4fdc8e5821d852a933963ba56b9b2fa8f68c68f (diff)
downloadlinux-878a3ee38d6e876093f742403316e91301303a3d.tar.xz
ARM: berlin: Add AHCI and SATA PHY nodes to BG2
Add DT nodes for the AHCI controller and SATA PHY found on Marvell Berlin2 SoCs. Acked-by: Antoine Ténart <antoine.tenart@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Diffstat (limited to 'arch/arm/boot/dts/berlin2.dtsi')
-rw-r--r--arch/arm/boot/dts/berlin2.dtsi39
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index 20e7c394a008..015a06c67c91 100644
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -311,6 +311,45 @@
};
};
+ ahci: sata@e90000 {
+ compatible = "marvell,berlin2-ahci", "generic-ahci";
+ reg = <0xe90000 0x1000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&chip CLKID_SATA>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sata0: sata-port@0 {
+ reg = <0>;
+ phys = <&sata_phy 0>;
+ status = "disabled";
+ };
+
+ sata1: sata-port@1 {
+ reg = <1>;
+ phys = <&sata_phy 1>;
+ status = "disabled";
+ };
+ };
+
+ sata_phy: phy@e900a0 {
+ compatible = "marvell,berlin2-sata-phy";
+ reg = <0xe900a0 0x200>;
+ clocks = <&chip CLKID_SATA>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+
+ sata-phy@0 {
+ reg = <0>;
+ };
+
+ sata-phy@1 {
+ reg = <1>;
+ };
+ };
+
chip: chip-control@ea0000 {
compatible = "marvell,berlin2-chip-ctrl";
#clock-cells = <1>;