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authorTony Lindgren <tony@atomide.com>2021-03-10 15:03:45 +0300
committerTony Lindgren <tony@atomide.com>2021-03-10 15:04:07 +0300
commit785d943c768ef631271d1ed5caef1c162e001d6b (patch)
tree224145a0b0c8d71cc88410f5155dc8a82623c26f /arch/arm/boot/dts/dra7.dtsi
parentc761028ef5e27f477fe14d2b134164c584fc21ee (diff)
downloadlinux-785d943c768ef631271d1ed5caef1c162e001d6b.tar.xz
ARM: dts: Configure interconnect target module for dra7 pcie
We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Tested-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/dra7.dtsi')
-rw-r--r--arch/arm/boot/dts/dra7.dtsi34
1 files changed, 30 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 39614c7232bf..f7e40227d7de 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -166,8 +166,21 @@
l4_per3: interconnect@48800000 {
};
- axi@0 {
- compatible = "simple-bus";
+ /*
+ * Register access seems to have complex dependencies and also
+ * seems to need an enabled phy. See the TRM chapter for "Table
+ * 26-678. Main Sequence PCIe Controller Global Initialization"
+ * and also dra7xx_pcie_probe().
+ */
+ axi0: target-module@51000000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ power-domains = <&prm_l3init>;
+ resets = <&prm_l3init 0>;
+ reset-names = "rstctrl";
+ clocks = <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 0>,
+ <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>,
+ <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>;
+ clock-names = "fck", "phy-clk", "phy-clk-div";
#size-cells = <1>;
#address-cells = <1>;
ranges = <0x51000000 0x51000000 0x3000>,
@@ -229,8 +242,21 @@
};
};
- axi@1 {
- compatible = "simple-bus";
+ /*
+ * Register access seems to have complex dependencies and also
+ * seems to need an enabled phy. See the TRM chapter for "Table
+ * 26-678. Main Sequence PCIe Controller Global Initialization"
+ * and also dra7xx_pcie_probe().
+ */
+ axi1: target-module@51800000 {
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ clocks = <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 0>,
+ <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>,
+ <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>;
+ clock-names = "fck", "phy-clk", "phy-clk-div";
+ power-domains = <&prm_l3init>;
+ resets = <&prm_l3init 1>;
+ reset-names = "rstctrl";
#size-cells = <1>;
#address-cells = <1>;
ranges = <0x51800000 0x51800000 0x3000>,