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authorRoger Quadros <rogerq@ti.com>2016-02-23 19:37:17 +0300
committerTony Lindgren <tony@atomide.com>2016-02-26 21:12:45 +0300
commit488f270d90e17738a35c2b41c1c3f708f614fdb3 (patch)
tree62cf27f3cd4ce2e37167725a64222b67aa17448e /arch/arm/boot/dts/dra72-evm.dts
parent92e963f50fc74041b5e9e744c330dca48e04f08d (diff)
downloadlinux-488f270d90e17738a35c2b41c1c3f708f614fdb3.tar.xz
ARM: dts: dra7: Fix NAND device nodes
Add compatible id, GPMC register resource and interrupt resource to NAND controller nodes. The GPMC node will provide an interrupt controller for the NAND IRQs. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/dra72-evm.dts')
-rw-r--r--arch/arm/boot/dts/dra72-evm.dts6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 00b12002c07c..6cf211bccd31 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -492,13 +492,17 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_default>;
- ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
+ ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
nand@0,0 {
/* To use NAND, DIP switch SW5 must be set like so:
* SW5.1 (NAND_SELn) = ON (LOW)
* SW5.9 (GPMC_WPN) = OFF (HIGH)
*/
+ compatible = "ti,omap2-nand";
reg = <0 0 4>; /* device IO registers */
+ interrupt-parent = <&gpmc>;
+ interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+ <1 IRQ_TYPE_NONE>; /* termcount */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;