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authorKrzysztof Kozlowski <krzk@kernel.org>2019-04-15 21:05:07 +0300
committerKrzysztof Kozlowski <krzk@kernel.org>2019-04-24 20:52:30 +0300
commitbe00300147ae3c0b2fa4dbc5f00d4332a8d00fac (patch)
treec1599bc8fcb6ca2cb10d943c7219404d6034e0c8 /arch/arm/boot/dts/exynos5250.dtsi
parent8cc76b1c75722196fb3d7ffe67cbfeb721a7b0e3 (diff)
downloadlinux-be00300147ae3c0b2fa4dbc5f00d4332a8d00fac.tar.xz
ARM: dts: exynos: Move pmu and timer nodes out of soc
The ARM PMU and ARM architected timer nodes are part of ARM CPU design therefore they should not be inside the soc node. This also fixes DTC W=1 warnings like: arch/arm/boot/dts/exynos3250.dtsi:106.21-135.5: Warning (simple_bus_reg): /soc/fixed-rate-clocks: missing or empty reg/ranges property arch/arm/boot/dts/exynos3250.dtsi:676.7-680.5: Warning (simple_bus_reg): /soc/pmu: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Diffstat (limited to 'arch/arm/boot/dts/exynos5250.dtsi')
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi40
1 files changed, 20 insertions, 20 deletions
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 80986b97dfe5..d5e0392b409e 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -157,6 +157,12 @@
};
};
+ pmu {
+ compatible = "arm,cortex-a15-pmu";
+ interrupt-parent = <&combiner>;
+ interrupts = <1 2>, <22 4>;
+ };
+
soc: soc {
sysram@2020000 {
compatible = "mmio-sram";
@@ -227,20 +233,6 @@
power-domains = <&pd_mau>;
};
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- /*
- * Unfortunately we need this since some versions
- * of U-Boot on Exynos don't set the CNTFRQ register,
- * so we need the value from DT.
- */
- clock-frequency = <24000000>;
- };
-
mct@101c0000 {
compatible = "samsung,exynos4210-mct";
reg = <0x101C0000 0x800>;
@@ -265,12 +257,6 @@
};
};
- pmu {
- compatible = "arm,cortex-a15-pmu";
- interrupt-parent = <&combiner>;
- interrupts = <1 2>, <22 4>;
- };
-
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x11400000 0x1000>;
@@ -1097,6 +1083,20 @@
};
};
};
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ /*
+ * Unfortunately we need this since some versions
+ * of U-Boot on Exynos don't set the CNTFRQ register,
+ * so we need the value from DT.
+ */
+ clock-frequency = <24000000>;
+ };
};
&dp {