summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/exynos54xx.dtsi
diff options
context:
space:
mode:
authorMarek Szyprowski <m.szyprowski@samsung.com>2019-08-28 15:10:04 +0300
committerKrzysztof Kozlowski <krzk@kernel.org>2019-10-02 18:39:57 +0300
commit9c8238b85c26f7cb349063ce3be9dd05c15c748c (patch)
treeddbfd618695f8bc56cb235115467a208dd3fc118 /arch/arm/boot/dts/exynos54xx.dtsi
parent54ecb8f7028c5eb3d740bb82b0f1d90f2df63c5c (diff)
downloadlinux-9c8238b85c26f7cb349063ce3be9dd05c15c748c.tar.xz
ARM: dts: exynos: Add support ARM architected timers on Exynos5
All CortexA7/A15 based Exynos5 SoCs have ARM architected timers, so enable support for them directly in the base dtsi. None of the known firmware properly configures CNTFRQ arch timer register, so force clock frequency to 24MHz, which is the only configuration supported by the remaining clock drivers so far. Stock firmware for Peach Pit and Pi Chromebooks also doesn't reset properly other arch timer registers, so add respective properties indicating that. Other Exynos5-based boards behaves correctly in this area, what finally allows to enable support for KVM-based virtualization. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/exynos54xx.dtsi')
-rw-r--r--arch/arm/boot/dts/exynos54xx.dtsi9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi
index 9c3b63b7cac6..02d34957cd83 100644
--- a/arch/arm/boot/dts/exynos54xx.dtsi
+++ b/arch/arm/boot/dts/exynos54xx.dtsi
@@ -45,6 +45,15 @@
status = "disabled";
};
+ timer: timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <24000000>;
+ };
+
soc: soc {
sysram@2020000 {
compatible = "mmio-sram";