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authorAnson Huang <b20788@freescale.com>2014-12-05 11:23:49 +0300
committerShawn Guo <shawn.guo@linaro.org>2015-01-05 15:43:49 +0300
commit4c61a1e75cd9247c624de8481efe85208b97ac85 (patch)
treedf06592b970971a9fb8a01d35da66d6acf312af3 /arch/arm/boot/dts/imx6dl.dtsi
parenteabb3227d912f554237bf2a0920108cb6e372eb0 (diff)
downloadlinux-4c61a1e75cd9247c624de8481efe85208b97ac85.tar.xz
ARM: dts: imx6dl: correct cpufreq volt/freq table
Currently the cpufreq volt/freq table we used is for LDO enable mode, according to latest datasheet Rev. 3, 03/2014, the volt/freq table is as below: LDO enabled(min value): 996MHz: VDDARM: 1.225V, VDDSOC: 1.150V; 792MHz: VDDARM: 1.150V, VDDSOC: 1.150V; 396MHz: VDDARM: 1.050V, VDDSOC: 1.150V; LDO bypassed(min value): 996MHz: VDDARM: 1.250V, VDDSOC: 1.150V; 792MHz: VDDARM: 1.150V, VDDSOC: 1.150V; 396MHz: VDDARM: 1.050V, VDDSOC: 1.150V; Adding 25mV to cover board IR drop, for LDO enabled mode of 996MHz, VDDARM should be 1.250V, so this patch updates it. Signed-off-by: Anson Huang <b20788@freescale.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6dl.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6dl.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 1ac2fe732867..f94bf72832af 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -28,7 +28,7 @@
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
- 996000 1275000
+ 996000 1250000
792000 1175000
396000 1075000
>;