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authorShawn Guo <shawn.guo@linaro.org>2013-02-20 06:32:52 +0400
committerShawn Guo <shawn.guo@linaro.org>2013-04-09 18:52:50 +0400
commite16415313c9b00b1adc313e85c2c8a81febe0b98 (patch)
treeb1e804b1bb647f3984036d9f9befbe53023bc519 /arch/arm/boot/dts/imx6q-sabrelite.dts
parent36dffd8f49bc1364998db81bee739ea4574d88f7 (diff)
downloadlinux-e16415313c9b00b1adc313e85c2c8a81febe0b98.tar.xz
pinctrl: imx: move hard-coding data into device tree
Currently, all imx pinctrl drivers maintain a big array of struct imx_pin_reg which hard-codes data like register offset and mux mode setting for each pin function. Every time a new imx SoC support is added, we need to add such a big mount of data. With moving to single kernel build, it's only matter of time to be blamed on memory consuming. With DTC pre-processor support in place, the patch moves all these data into device tree by redefining the PIN_FUNC_ID in imxXX-pinfunc.h and changing the PIN_FUNC_ID parsing code a little bit. The pin id gets re-numbered based on mux register offset, or config register offset if the pin has no mux register, so that kernel can identify the pin id from register offsets provided by device tree. As a bonus point of the change, those arbitrary magic numbers standing for particular PIN_FUNC_ID in device tree sources are now replaced by macros to improve the readability of dts files. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dong Aisheng <dong.aisheng@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6q-sabrelite.dts')
-rw-r--r--arch/arm/boot/dts/imx6q-sabrelite.dts16
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index e119ba3697bf..6a000666c147 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -91,14 +91,14 @@
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
- 1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
- 1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
- 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
- 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
- 152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
- 1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
- 1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
- 953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
+ MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x80000000
+ MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x80000000
+ MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000
+ MX6Q_PAD_EIM_D22__GPIO3_IO22 0x80000000
+ MX6Q_PAD_EIM_D23__GPIO3_IO23 0x80000000
+ MX6Q_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
+ MX6Q_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
+ MX6Q_PAD_GPIO_0__CCM_CLKO1 0x80000000
>;
};
};