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authorTim Harvey <tharvey@gateworks.com>2014-09-09 10:07:29 +0400
committerShawn Guo <shawn.guo@freescale.com>2014-09-16 06:27:20 +0400
commit73e005c111bc3f77ca3793d465539a11e7604c71 (patch)
treee91dc98592e46dfc7f3ff59e798b48ba5818cb18 /arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
parent326cdb16552c3670fefd583d94fe797e776130b6 (diff)
downloadlinux-73e005c111bc3f77ca3793d465539a11e7604c71.tar.xz
ARM: dts: imx: ventana: configure padconf for all pins
Follow the convention of configuring padconf for all pins and not leaving any 0x80000000 to leave them un-configured. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-gw53xx.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw53xx.dtsi40
1 files changed, 20 insertions, 20 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index 2074df6f8095..e6e298bb7576 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -247,25 +247,25 @@
imx6qdl-gw53xx {
pinctrl_hog: hoggrp {
fsl,pins = <
- MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* PCIE6EXP_DIO0 */
- MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* PCIE6EXP_DIO1 */
- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */
- MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_SHDN */
- MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */
- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */
- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */
+ MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x4001b0b0 /* PCIE6EXP_DIO0 */
+ MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 /* PCIE6EXP_DIO1 */
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0001b0b0 /* OTG_PWR_EN */
+ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x4001b0b0 /* GPS_SHDN */
+ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b0b0 /* GPS_PPS */
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0001b0b0 /* PCIE IRQ */
+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x0001b0b0 /* PCIE RST */
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */
- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */
- MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000 /* PMIC_IRQ# */
- MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 /* HUB_RST# */
- MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIE_WDIS# */
- MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* ACCEL_IRQ# */
- MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */
- MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x80000000 /* USBOTG_OC# */
- MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */
- MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */
- MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* TOUCH_IRQ# */
- MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_DET# */
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* HUB_RST# */
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIE_WDIS# */
+ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x0001b0b0 /* ACCEL_IRQ# */
+ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x0001b0b0 /* user1 led */
+ MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0001b0b0 /* USBOTG_OC# */
+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x0001b0b0 /* user2 led */
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0001b0b0 /* user3 led */
+ MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x0001b0b0 /* TOUCH_IRQ# */
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x0001b0b0 /* SD3_DET# */
>;
};
@@ -301,8 +301,8 @@
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
>;
};