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authorAnson Huang <Anson.Huang@nxp.com>2019-07-18 12:15:05 +0300
committerShawn Guo <shawnguo@kernel.org>2019-07-23 10:47:46 +0300
commit211ded7861466dd443e61ad29ec34ce93e5a3e38 (patch)
tree365ee620735a29589aebbe97eee4bdeaad76d052 /arch/arm/boot/dts/imx6sx.dtsi
parent9461e35f84184662e395ee4c0222687a8f121586 (diff)
downloadlinux-211ded7861466dd443e61ad29ec34ce93e5a3e38.tar.xz
ARM: dts: imx6sx: move GIC to right location in DT
GIC is inside of SoC from architecture perspective, it should be located inside of soc node in DT. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6sx.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6sx.dtsi18
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index bb25add90f19..fe00f9a8accd 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -90,15 +90,6 @@
};
};
- intc: interrupt-controller@a01000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x00a01000 0x1000>,
- <0x00a00100 0x100>;
- interrupt-parent = <&intc>;
- };
-
ckil: clock-ckil {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -181,6 +172,15 @@
clocks = <&clks IMX6SX_CLK_OCRAM>;
};
+ intc: interrupt-controller@a01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00a01000 0x1000>,
+ <0x00a00100 0x100>;
+ interrupt-parent = <&intc>;
+ };
+
L2: l2-cache@a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;