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| author | Shawn Guo <shawnguo@kernel.org> | 2018-12-10 05:32:51 +0300 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2018-12-10 05:32:51 +0300 |
| commit | 2e8566106d284badf6ec94509f77fdf7725d04b4 (patch) | |
| tree | 21e6edc1754cad60e06ed2152548815c0acb6846 /arch/arm/boot/dts/imx7d-pico.dtsi | |
| parent | 79da07dec740a42c70963ebacbd2bf8866af9e20 (diff) | |
| parent | f15096f12a4e9340168df5fdd9201aa8ed60d59e (diff) | |
| download | linux-2e8566106d284badf6ec94509f77fdf7725d04b4.tar.xz | |
Merge tag 'imx-fixes-4.20-3' into imx7d/pico
i.MX fixes for 4.20, round 3:
- A couple of fixes on imx7d-pico and imx7d-nitrogen7 boards to correct
the description of the Wifi clock.
- Change SW2ISO count to get a safer ARM LDO ramp-up time, so that
different boards can be covered. This fixes the ARM LDO failure seen
on some customer boards.
Diffstat (limited to 'arch/arm/boot/dts/imx7d-pico.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx7d-pico.dtsi | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx7d-pico.dtsi b/arch/arm/boot/dts/imx7d-pico.dtsi index 4846df0783c1..934a019f341e 100644 --- a/arch/arm/boot/dts/imx7d-pico.dtsi +++ b/arch/arm/boot/dts/imx7d-pico.dtsi @@ -101,6 +101,19 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + usdhc2_pwrseq: usdhc2_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&clks IMX7D_CLKO2_ROOT_DIV>; + clock-names = "ext_clock"; + }; +}; + +&clks { + assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>, + <&clks IMX7D_CLKO2_ROOT_DIV>; + assigned-clock-parents = <&clks IMX7D_CKIL>; + assigned-clock-rates = <0>, <32768>; }; &i2c4 { @@ -200,12 +213,13 @@ &usdhc2 { /* Wifi SDIO */ pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi_clk>; no-1-8-v; non-removable; keep-power-in-suspend; wakeup-source; vmmc-supply = <®_ap6212>; + mmc-pwrseq = <&usdhc2_pwrseq>; status = "okay"; }; @@ -302,6 +316,12 @@ }; &iomuxc_lpsr { + pinctrl_wifi_clk: wificlkgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x7d + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 |