summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/lpc32xx.dtsi
diff options
context:
space:
mode:
authorVladimir Zapolskiy <vz@mleia.com>2015-10-18 00:35:55 +0300
committerVladimir Zapolskiy <vz@mleia.com>2015-11-18 19:01:19 +0300
commitf83ee67fcf8d743e7fbcb08c70fcd32c253bb2fa (patch)
treed9dd4801f0f2505b42f621030d57ce1287813aa5 /arch/arm/boot/dts/lpc32xx.dtsi
parentcae59490674cf8dab153c6b1350247228b3fc972 (diff)
downloadlinux-f83ee67fcf8d743e7fbcb08c70fcd32c253bb2fa.tar.xz
arm: dts: lpc32xx: add external memory controller device node
The change adds a description of ARM PrimeCell PL175 memory controller, which is found on NXP LPC32xx SoCs. The controller supports up to 4 static memory devices mapped to 0xE000 0000 - 0xE3FF FFFF physical memory area. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Diffstat (limited to 'arch/arm/boot/dts/lpc32xx.dtsi')
-rw-r--r--arch/arm/boot/dts/lpc32xx.dtsi16
1 files changed, 15 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index be829926f860..a595a4b772d4 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -32,7 +32,8 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
- ranges = <0x20000000 0x20000000 0x30000000>;
+ ranges = <0x20000000 0x20000000 0x30000000>,
+ <0xe0000000 0xe0000000 0x04000000>;
/*
* Enable either SLC or MLC
@@ -86,6 +87,19 @@
interrupts = <0x1d 0>;
};
+ emc: memory-controller@31080000 {
+ compatible = "arm,pl175", "arm,primecell";
+ reg = <0x31080000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0xe0000000 0x01000000>,
+ <1 0xe1000000 0x01000000>,
+ <2 0xe2000000 0x01000000>,
+ <3 0xe3000000 0x01000000>;
+ status = "disabled";
+ };
+
apb {
#address-cells = <1>;
#size-cells = <1>;