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authorLinus Torvalds <torvalds@linux-foundation.org>2016-03-25 05:01:38 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2016-03-25 05:01:38 +0300
commit8a20a04bda46625f8dc7e6bb8c2e4f5a480965fd (patch)
treefe51424b24e43653b945b268438a92c2a45030d7 /arch/arm/boot/dts/ls1021a.dtsi
parent732b84eece43bca56d2b4b28f5d2109cd30a6a32 (diff)
parent6fe35ab77de9f38e9319c8def0597709759f99fd (diff)
downloadlinux-8a20a04bda46625f8dc7e6bb8c2e4f5a480965fd.tar.xz
Merge tag 'armsoc-dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull more ARM DT changes from Arnd Bergmann: "Here are some final updates for ARM SoC specific dts files: - The i.MX changes were sent relatively late, and had a dependency on the clk tree, so I delayed that a bit. Support for the new i.MX6qp SoC and a couple of new boards is added in this branch. - Uniphier renames a few files to match the final product names that were decided by the company, kudos to the kernel developer(s) for getting support upstream before the product release. Also two boards are added. The patches were posted early enough and nice overall, but we forgot to apply them and decided to give it some more time in linux-next - at91 has two small bug fixes" * tag 'armsoc-dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (83 commits) ARM: dts: at91: sama5d4 Xplained: don't disable hsmci regulator ARM: dts: at91: sama5d3 Xplained: don't disable hsmci regulator ARM: dts: uniphier: add pinmux node for I2C ch4 ARM: dts: uniphier: add @{address} to EEPROM node ARM: dts: uniphier: add PH1-Pro4 Sanji board support ARM: dts: uniphier: add PH1-Pro4 Ace board support ARM: dts: uniphier: enable I2C channel 2 of ProXstream2 Gentil board ARM: dts: uniphier: add EEPROM node for ProXstream2 Gentil board ARM: dts: uniphier: add reference clock nodes ARM: dts: uniphier: rework UniPhier System Bus nodes ARM: dts: uniphier: factor out ranges property of support card arm64: dts: uniphier: rename PH1-LD10 to PH1-LD20 ARM: dts: imx53-qsb: Fix gpio button polarity ARM: dts: vfxxx: Add DAC node for Vybrid SoC ARM: dts: imx6q: add missing links between ipu2 and mipi dsi ARM: dts: imx: Add support for Advantech/GE B850v3 ARM: dts: imx: Add support for Advantech/GE B650v3 ARM: dts: imx: Add support for Advantech/GE B450v3 ARM: dts: imx: Add support for Advantech/GE Bx50v3 ARM: dts: imx: Add Advantech BA-16 Qseven module ...
Diffstat (limited to 'arch/arm/boot/dts/ls1021a.dtsi')
-rw-r--r--arch/arm/boot/dts/ls1021a.dtsi44
1 files changed, 44 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index ecf12dc22595..726372d3adc0 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -572,5 +572,49 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
};
+
+ pcie@3400000 {
+ compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
+ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ fsl,pcie-scfg = <&scfg 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pcie@3500000 {
+ compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
+ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,pcie-scfg = <&scfg 1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
};