diff options
author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2023-05-16 23:30:29 +0300 |
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committer | Neil Armstrong <neil.armstrong@linaro.org> | 2023-05-31 11:55:46 +0300 |
commit | 98b503c7fb13a17a47d8ebf15fa8f7c10118e75c (patch) | |
tree | 5d1353f3545f549bb0f4ff0343ea375f8fe073b8 /arch/arm/boot/dts/meson8.dtsi | |
parent | d542ce8d4769cdef6a7bc3437e59cfed9c68f0e4 (diff) | |
download | linux-98b503c7fb13a17a47d8ebf15fa8f7c10118e75c.tar.xz |
ARM: dts: meson8: correct uart_B and uart_C clock references
On Meson8 uart_B and uart_C do not work, because they are relying on
incorrect clocks. Change the references of pclk to the correct CLKID
(UART1 for uart_B and UART2 for uart_C), to allow use of the two uarts.
This was originally reported by Hans-Frieder Vogt for Meson8b [0], but
the same bug is also present in meson8.dtsi
[0] https://lore.kernel.org/linux-amlogic/trinity-bf20bcb9-790b-4ab9-99e3-0831ef8257f4-1680878185420@3c-app-gmx-bap55/
Fixes: 57007bfb5469 ("ARM: dts: meson8: Fix the UART device-tree schema validation")
Reported-by: Hans-Frieder Vogt <hfdevel@gmx.net> # for meson8b.dtsi
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20230516203029.1031174-1-martin.blumenstingl@googlemail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/meson8.dtsi')
-rw-r--r-- | arch/arm/boot/dts/meson8.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 4f22ab451aae..59932fbfd5d5 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -769,13 +769,13 @@ &uart_B { compatible = "amlogic,meson8-uart"; - clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; + clocks = <&xtal>, <&clkc CLKID_UART1>, <&clkc CLKID_CLK81>; clock-names = "xtal", "pclk", "baud"; }; &uart_C { compatible = "amlogic,meson8-uart"; - clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; + clocks = <&xtal>, <&clkc CLKID_UART2>, <&clkc CLKID_CLK81>; clock-names = "xtal", "pclk", "baud"; }; |