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author | Tony Lindgren <tony@atomide.com> | 2019-12-12 20:46:11 +0300 |
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committer | Tony Lindgren <tony@atomide.com> | 2020-01-23 19:23:26 +0300 |
commit | fbb8bb8370f6fdaaaccf85201f4ee2a665aae42d (patch) | |
tree | c998a79a631c334e9d11010483a3a021b8732e89 /arch/arm/boot/dts/motorola-mapphone-common.dtsi | |
parent | 723a567f43b8ffa8089009bc8a260cc6f963661e (diff) | |
download | linux-fbb8bb8370f6fdaaaccf85201f4ee2a665aae42d.tar.xz |
ARM: dts: Configure omap4 rng to probe with ti-sysc
Add RNG interconnect data for omap4 similar to what dra7 has. The
clock is OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET at offset address 0x01c0,
which matches what dra7 also has with DRA7_L4SEC_CLKCTRL_INDEX(0x1c0).
Note that we need to also add the related l4_secure clock entries.
I've only added RNG, the others can be added as they get tested.
They are probably very similar to what we already have for dra7
in dra7_l4sec_clkctrl_regs[].
With the clock tagged CLKF_SOC_NONSEC, clock is set disabled for secure
devices and clk_get() will fail. Additionally we disable the RNG target
module on droid4 to avoid introducing new boot time warnings.
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/motorola-mapphone-common.dtsi')
-rw-r--r-- | arch/arm/boot/dts/motorola-mapphone-common.dtsi | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/motorola-mapphone-common.dtsi b/arch/arm/boot/dts/motorola-mapphone-common.dtsi index da6b107da84a..71e7ea903eb5 100644 --- a/arch/arm/boot/dts/motorola-mapphone-common.dtsi +++ b/arch/arm/boot/dts/motorola-mapphone-common.dtsi @@ -650,6 +650,11 @@ }; }; +/* RNG is used by secure mode and not accessible */ +&rng_target { + status = "disabled"; +}; + /* Configure pwm clock source for timers 8 & 9 */ &timer8 { assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>; |