summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/mt8127.dtsi
diff options
context:
space:
mode:
authorYingjoe Chen <yingjoe.chen@mediatek.com>2014-11-25 11:04:00 +0300
committerMatthias Brugger <matthias.bgg@gmail.com>2015-01-02 13:13:01 +0300
commite0bed0774538bdb2e82d6999c8ed9556116e8559 (patch)
tree668bdb522d3f9c9c33c43963fde69a955341c83b /arch/arm/boot/dts/mt8127.dtsi
parent97bf6af1f928216fd6c5a66e8a57bfa95a659672 (diff)
downloadlinux-e0bed0774538bdb2e82d6999c8ed9556116e8559.tar.xz
ARM: mediatek: Add sysirq in mt6589/mt8135/mt8127 dtsi
Add sysirq settings for mt6589/mt8135/mt8127 This also correct timer interrupt flag. The old setting works because boot loader already set polarity for timer interrupt. Without intpol support, the setting was not changed so gic can get the irq correctly. Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch/arm/boot/dts/mt8127.dtsi')
-rw-r--r--arch/arm/boot/dts/mt8127.dtsi14
1 files changed, 12 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
index b24c0a2f3c44..a325404c714c 100644
--- a/arch/arm/boot/dts/mt8127.dtsi
+++ b/arch/arm/boot/dts/mt8127.dtsi
@@ -18,7 +18,7 @@
/ {
compatible = "mediatek,mt8127";
- interrupt-parent = <&gic>;
+ interrupt-parent = <&sysirq>;
cpus {
#address-cells = <1>;
@@ -76,15 +76,25 @@
compatible = "mediatek,mt8127-timer",
"mediatek,mt6577-timer";
reg = <0 0x10008000 0 0x80>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
clocks = <&system_clk>, <&rtc_clk>;
clock-names = "system-clk", "rtc-clk";
};
+ sysirq: interrupt-controller@10200100 {
+ compatible = "mediatek,mt8127-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10200100 0 0x1c>;
+ };
+
gic: interrupt-controller@10211000 {
compatible = "arm,cortex-a7-gic";
interrupt-controller;
#interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
reg = <0 0x10211000 0 0x1000>,
<0 0x10212000 0 0x1000>,
<0 0x10214000 0 0x2000>,