summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/omap4.dtsi
diff options
context:
space:
mode:
authorTony Lindgren <tony@atomide.com>2017-08-30 18:19:38 +0300
committerTony Lindgren <tony@atomide.com>2017-09-19 20:21:11 +0300
commitb0142a10db149daadbc2cc94c890dd00b3fa58ad (patch)
treeac6509e5ba1195f2ca3801b539803aec2c7b17a2 /arch/arm/boot/dts/omap4.dtsi
parentf0f838fd8cd53d8df8220b4081d7dec042ac9dd7 (diff)
downloadlinux-b0142a10db149daadbc2cc94c890dd00b3fa58ad.tar.xz
ARM: dts: Configure pmu without interrupt for omap4430
On omap4430, the PMU is not configure unlike on omap4460 because of the missing handling. The missing pmu node with the missing ti,hwmods entry will cause boot time errors when the legacy platform data is removed as the SoC interconnect code needs it. Note that this will only show up as a bug with "doesn't have mpu register target base" boot errors when the legacy platform data is removed. Let's fix the issue by configuring PMU but without the interrupts. Then when cross trigger interface (CTI) is supported, we can add interrupts also for omap4430. Cc: Jon Hunter <jonathanh@nvidia.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/omap4.dtsi')
-rw-r--r--arch/arm/boot/dts/omap4.dtsi11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 64d00f5893a6..47bc41954e2e 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -51,6 +51,17 @@
};
};
+ /*
+ * Note that 4430 needs cross trigger interface (CTI) supported
+ * before we can configure the interrupts. This means sampling
+ * events are not supported for pmu. Note that 4460 does not use
+ * CTI, see also 4460.dtsi.
+ */
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ ti,hwmods = "debugss";
+ };
+
gic: interrupt-controller@48241000 {
compatible = "arm,cortex-a9-gic";
interrupt-controller;