diff options
| author | Niklas Cassel <niklas.cassel@linaro.org> | 2019-01-24 16:00:47 +0300 |
|---|---|---|
| committer | Andy Gross <andy.gross@linaro.org> | 2019-02-07 00:53:17 +0300 |
| commit | 97131f85c08e024df49480ed499aae8fb754067f (patch) | |
| tree | 47c89a7707c56c679185061b03396bc942f2291f /arch/arm/boot/dts/qcom-ipq4019.dtsi | |
| parent | 40122db87778970c96062c9f49b42cdf6809bf94 (diff) | |
| download | linux-97131f85c08e024df49480ed499aae8fb754067f.tar.xz | |
ARM: dts: qcom: ipq4019: Fix MSI IRQ type
The databook clearly states that the MSI IRQ (msi_ctrl_int) is a level
triggered interrupt.
The msi_ctrl_int will be high for as long as any MSI status bit is set,
thus the IRQ type should be set to IRQ_TYPE_LEVEL_HIGH, causing the
IRQ handler to keep getting called, as long as any MSI status bit is set.
A git grep shows that ipq4019 is the only SoC using snps,dw-pcie that has
configured this IRQ incorrectly.
Not having the correct IRQ type defined will cause us to lose interrupts,
which in turn causes timeouts in the PCIe endpoint drivers.
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/qcom-ipq4019.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 19635f91e2c4..48b3cb474ba0 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -398,7 +398,7 @@ ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000 0x82000000 0 0x40300000 0x40300000 0 0x400000>; - interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; |