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authorKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>2022-05-26 23:42:48 +0300
committerBjorn Andersson <bjorn.andersson@linaro.org>2022-06-30 06:23:03 +0300
commit31b2edcab4d153145354c4333a6be5209e185598 (patch)
treec36b1e25b2e800ec6709a990052ff8ccefa27649 /arch/arm/boot/dts/qcom-ipq8064.dtsi
parent7afef282d7453ded3b31f71771a31b34dda51aff (diff)
downloadlinux-31b2edcab4d153145354c4333a6be5209e185598.tar.xz
ARM: dts: qcom: adjust whitespace around '='
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220526204248.832139-2-krzysztof.kozlowski@linaro.org
Diffstat (limited to 'arch/arm/boot/dts/qcom-ipq8064.dtsi')
-rw-r--r--arch/arm/boot/dts/qcom-ipq8064.dtsi32
1 files changed, 16 insertions, 16 deletions
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 4022ed9df988..4b475d98343c 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -1184,16 +1184,16 @@
ranges;
sdcc1: mmc@12400000 {
- status = "disabled";
- compatible = "arm,pl18x", "arm,primecell";
+ status = "disabled";
+ compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
- reg = <0x12400000 0x2000>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x12400000 0x2000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
- clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <8>;
- max-frequency = <96000000>;
+ clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <8>;
+ max-frequency = <96000000>;
non-removable;
cap-sd-highspeed;
cap-mmc-highspeed;
@@ -1204,18 +1204,18 @@
};
sdcc3: mmc@12180000 {
- compatible = "arm,pl18x", "arm,primecell";
+ compatible = "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00051180>;
- status = "disabled";
- reg = <0x12180000 0x2000>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ reg = <0x12180000 0x2000>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cmd_irq";
- clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
- clock-names = "mclk", "apb_pclk";
- bus-width = <8>;
+ clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
- max-frequency = <192000000>;
+ max-frequency = <192000000>;
sd-uhs-sdr104;
sd-uhs-ddr50;
vqmmc-supply = <&vsdcc_fixed>;