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authorChris Brandt <chris.brandt@renesas.com>2019-06-04 23:09:13 +0300
committerSimon Horman <horms+renesas@verge.net.au>2019-06-21 10:45:34 +0300
commite23391f36ce14719768ad5395e93a54fec7edf5a (patch)
treed0d9d8429c5859dd869c0cd40f835944fe3cdf42 /arch/arm/boot/dts/r7s9210.dtsi
parent1de78ccbda7835da6e1a75d5860267afb4f393f3 (diff)
downloadlinux-e23391f36ce14719768ad5395e93a54fec7edf5a.tar.xz
ARM: dts: r7s9210: Add IRQC device node
Enable support for the IRQC on RZ/A2M, which is a small front-end to the GIC. This allows to use up to 8 external interrupts with configurable sense select. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r7s9210.dtsi')
-rw-r--r--arch/arm/boot/dts/r7s9210.dtsi19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi
index 3d0bbc1f4543..72b79770e336 100644
--- a/arch/arm/boot/dts/r7s9210.dtsi
+++ b/arch/arm/boot/dts/r7s9210.dtsi
@@ -473,6 +473,25 @@
reg = <0xfcfe8004 4>;
};
+ irqc: interrupt-controller@fcfef800 {
+ compatible = "renesas,r7s9210-irqc",
+ "renesas,rza1-irqc";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0xfcfef800 0x6>;
+ interrupt-map =
+ <0 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <7 0>;
+ };
+
pinctrl: pin-controller@fcffe000 {
compatible = "renesas,r7s9210-pinctrl";
reg = <0xfcffe000 0x1000>;