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authorHeiko Stuebner <heiko@sntech.de>2017-07-12 20:06:52 +0300
committerHeiko Stuebner <heiko@sntech.de>2017-09-22 12:17:59 +0300
commitec45ee8569acca970a9b310f7c99a9e3bfc1bc0b (patch)
treec4beb248f5af75635946599e927cd76e5d2a256b /arch/arm/boot/dts/rk3036.dtsi
parent6a4d02f88fa2b6c21d8ba645e690bdbfe6adcb1f (diff)
downloadlinux-ec45ee8569acca970a9b310f7c99a9e3bfc1bc0b.tar.xz
ARM: dts: rockchip: add rk3036 gpu node
The rk3036 uses a Mali400 GPU with one pixel processor. This adds the core node for it, which can be enabled in board devicetrees. Rockchip Mali GPUs use only one clock line for both bus and core. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rk3036.dtsi')
-rw-r--r--arch/arm/boot/dts/rk3036.dtsi19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 4916c65e0ace..5b084c0143ce 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -152,6 +152,25 @@
};
};
+ gpu: gpu@10090000 {
+ compatible = "rockchip,rk3036-mali", "arm,mali-400";
+ reg = <0x10090000 0x10000>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "pp0mmu";
+ assigned-clocks = <&cru SCLK_GPU>;
+ assigned-clock-rates = <100000000>;
+ clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
+ clock-names = "core", "bus";
+ resets = <&cru SRST_GPU>;
+ status = "disabled";
+ };
+
vop: vop@10118000 {
compatible = "rockchip,rk3036-vop";
reg = <0x10118000 0x19c>;