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authorHeiko Stuebner <heiko@sntech.de>2014-09-13 02:34:29 +0400
committerHeiko Stuebner <heiko@sntech.de>2014-10-20 13:52:24 +0400
commitbe8a77c54815b311485a348547ec80803ee9415b (patch)
tree772c123f75d053a75e81f35fe4c87b3b963cfe0d /arch/arm/boot/dts/rk3066a.dtsi
parentf114040e3ea6e07372334ade75d1ee0775c355e1 (diff)
downloadlinux-be8a77c54815b311485a348547ec80803ee9415b.tar.xz
ARM: dts: rockchip: add operating points and armclk references
Add basic OPP entries for current supported Rockchip SoCs. The operating points are currently very conservative, so individual boards may opt to redefine them. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'arch/arm/boot/dts/rk3066a.dtsi')
-rw-r--r--arch/arm/boot/dts/rk3066a.dtsi12
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index ad9c2db59670..8b11fbd58071 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -26,11 +26,21 @@
#size-cells = <0>;
enable-method = "rockchip,rk3066-smp";
- cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x0>;
+ operating-points = <
+ /* kHz uV */
+ 1008000 1075000
+ 816000 1025000
+ 600000 1025000
+ 504000 1000000
+ 312000 975000
+ >;
+ clock-latency = <40000>;
+ clocks = <&cru ARMCLK>;
};
cpu@1 {
device_type = "cpu";