summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/rk3066a.dtsi
diff options
context:
space:
mode:
authorHeiko Stuebner <heiko@sntech.de>2014-07-27 01:28:03 +0400
committerHeiko Stuebner <heiko@sntech.de>2014-07-27 01:28:03 +0400
commitff84b90ecd1cfd00af3d1832fd8bf3c18e555d4e (patch)
treedbd4468bb2717a7ee6adde1690b932036668cbca /arch/arm/boot/dts/rk3066a.dtsi
parent6e4b3b4b66dd6e7f4980a6626d54a532deb47517 (diff)
downloadlinux-ff84b90ecd1cfd00af3d1832fd8bf3c18e555d4e.tar.xz
ARM: dts: rockchip: oder nodes by register address
To create some sort of ordering of nodes, they are suggested to be ordered by their register address. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rk3066a.dtsi')
-rw-r--r--arch/arm/boot/dts/rk3066a.dtsi48
1 files changed, 24 insertions, 24 deletions
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 3198394429c2..21b87dece38c 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -40,30 +40,6 @@
};
};
- timer@20038000 {
- compatible = "snps,dw-apb-timer-osc";
- reg = <0x20038000 0x100>;
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
- clock-names = "timer", "pclk";
- };
-
- timer@2003a000 {
- compatible = "snps,dw-apb-timer-osc";
- reg = <0x2003a000 0x100>;
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
- clock-names = "timer", "pclk";
- };
-
- timer@2000e000 {
- compatible = "snps,dw-apb-timer-osc";
- reg = <0x2000e000 0x100>;
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
- clock-names = "timer", "pclk";
- };
-
sram: sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x10000>;
@@ -86,6 +62,30 @@
#reset-cells = <1>;
};
+ timer@2000e000 {
+ compatible = "snps,dw-apb-timer-osc";
+ reg = <0x2000e000 0x100>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
+ clock-names = "timer", "pclk";
+ };
+
+ timer@20038000 {
+ compatible = "snps,dw-apb-timer-osc";
+ reg = <0x20038000 0x100>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
+ clock-names = "timer", "pclk";
+ };
+
+ timer@2003a000 {
+ compatible = "snps,dw-apb-timer-osc";
+ reg = <0x2003a000 0x100>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
+ clock-names = "timer", "pclk";
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3066a-pinctrl";
rockchip,grf = <&grf>;