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authorHeiko Stuebner <heiko.stuebner@bq.com>2018-11-07 19:12:24 +0300
committerHeiko Stuebner <heiko@sntech.de>2018-11-27 17:11:36 +0300
commit0222aac4486e7bf5b37defa7fd03e3b2c52fe2be (patch)
treecca31f37c85dcc385bee798c947bae294bfe5b6f /arch/arm/boot/dts/rk3188.dtsi
parentabcee7a86373144249adec203cbaa98770101ce8 (diff)
downloadlinux-0222aac4486e7bf5b37defa7fd03e3b2c52fe2be.tar.xz
ARM: dts: rockchip: add cpu-core resets for rk3188
Specify the reset handles for each cpu core. Signed-off-by: Heiko Stuebner <heiko.stuebner@bq.com>
Diffstat (limited to 'arch/arm/boot/dts/rk3188.dtsi')
-rw-r--r--arch/arm/boot/dts/rk3188.dtsi4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 9d8c4c560e51..f1f7a36b46d4 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -26,6 +26,7 @@
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
operating-points-v2 = <&cpu0_opp_table>;
+ resets = <&cru SRST_CORE0>;
};
cpu@1 {
device_type = "cpu";
@@ -33,6 +34,7 @@
next-level-cache = <&L2>;
reg = <0x1>;
operating-points-v2 = <&cpu0_opp_table>;
+ resets = <&cru SRST_CORE1>;
};
cpu@2 {
device_type = "cpu";
@@ -40,6 +42,7 @@
next-level-cache = <&L2>;
reg = <0x2>;
operating-points-v2 = <&cpu0_opp_table>;
+ resets = <&cru SRST_CORE2>;
};
cpu@3 {
device_type = "cpu";
@@ -47,6 +50,7 @@
next-level-cache = <&L2>;
reg = <0x3>;
operating-points-v2 = <&cpu0_opp_table>;
+ resets = <&cru SRST_CORE3>;
};
};