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authorHeiko Stuebner <heiko@sntech.de>2017-01-19 19:04:44 +0300
committerHeiko Stuebner <heiko@sntech.de>2017-01-19 19:04:44 +0300
commitec7c98ec9b8dd2c04ed75cad88e91eebedbb1a25 (patch)
treecb10a30c738262fc288621681223ec6ab2e796ad /arch/arm/boot/dts/rk3188.dtsi
parente9e79d5395b2e60a03811073e0aedfbd7fa0bc57 (diff)
downloadlinux-ec7c98ec9b8dd2c04ed75cad88e91eebedbb1a25.tar.xz
ARM: dts: rockchip: add soc-specific uart compatibles for rk3066/rk3188
The serial IPs in Rockchip socs are based on Designware uarts and thus bind against the snps,dw-apb-uart compatible. On all newer socs we also carry around per-soc compatibles that allow us to have more specific drivers in the future - if needed. The cortex-a9 socs rk3066 and rk3188 that were added first don't have those yet, so add them for completenes sake. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rk3188.dtsi')
-rw-r--r--arch/arm/boot/dts/rk3188.dtsi4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 869e189331ec..cf91254d0a43 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -599,21 +599,25 @@
};
&uart0 {
+ compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>;
};
&uart1 {
+ compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer>;
};
&uart2 {
+ compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
};
&uart3 {
+ compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
pinctrl-names = "default";
pinctrl-0 = <&uart3_xfer>;
};