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authorBrian Norris <computersforpeace@gmail.com>2016-05-06 04:02:44 +0300
committerHeiko Stuebner <heiko@sntech.de>2016-05-30 10:42:35 +0300
commit9a205e33d0dc81121d1a2417b33b55682b81b84d (patch)
tree3320a5e8edd7f3ef23d76723b971a3f2e643f908 /arch/arm/boot/dts/rk3288-veyron.dtsi
parent1a695a905c18548062509178b98bc91e67510864 (diff)
downloadlinux-9a205e33d0dc81121d1a2417b33b55682b81b84d.tar.xz
ARM: dts: rockchip: add SPI flash node for rk3288-veyron
This is a standard binding for describing SPI flash that can be identified by reading their JEDEC ID. Let's use it. Tested on Veyron Jaq. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rk3288-veyron.dtsi')
-rw-r--r--arch/arm/boot/dts/rk3288-veyron.dtsi6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
index b2557bf5a58f..5e4c690c7d4f 100644
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
@@ -383,6 +383,12 @@
status = "okay";
rx-sample-delay-ns = <12>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
};
&tsadc {