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authorGeert Uytterhoeven <geert+renesas@glider.be>2015-01-06 22:56:05 +0300
committerSimon Horman <horms+renesas@verge.net.au>2015-02-24 00:30:41 +0300
commit56a215d66b1eee870a6b90a8c245dfc3e503a137 (patch)
treedaf832e896a1eb01d0ae76d64e84f1c6a6073ba9 /arch/arm/boot/dts/sh73a0.dtsi
parent8ac627fa8ef0f98f914690515aa3bf376d7a880d (diff)
downloadlinux-56a215d66b1eee870a6b90a8c245dfc3e503a137.tar.xz
ARM: shmobile: sh73a0 dtsi: Add missing INTCA0 clock for irqpin module
This clock drives the irqpin controller modules. Before, it was assumed enabled by the bootloader or reset state. By making it available to the driver, we make sure it gets enabled when needed, and allow it to be managed by system or runtime PM. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/sh73a0.dtsi')
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 076708797ef6..08f736d52179 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -94,6 +94,7 @@
0 6 IRQ_TYPE_LEVEL_HIGH
0 7 IRQ_TYPE_LEVEL_HIGH
0 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
control-parent;
};
@@ -114,6 +115,7 @@
0 14 IRQ_TYPE_LEVEL_HIGH
0 15 IRQ_TYPE_LEVEL_HIGH
0 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
control-parent;
};
@@ -134,6 +136,7 @@
0 22 IRQ_TYPE_LEVEL_HIGH
0 23 IRQ_TYPE_LEVEL_HIGH
0 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
control-parent;
};
@@ -154,6 +157,7 @@
0 30 IRQ_TYPE_LEVEL_HIGH
0 31 IRQ_TYPE_LEVEL_HIGH
0 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
control-parent;
};
@@ -698,5 +702,16 @@
clock-output-names =
"iic3", "iic4", "keysc";
};
+ mstp5_clks: mstp5_clks@e6150144 {
+ compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
+ reg = <0xe6150144 4>, <0xe615003c 4>;
+ clocks = <&cpg_clocks SH73A0_CLK_HP>;
+ #clock-cells = <1>;
+ clock-indices = <
+ SH73A0_CLK_INTCA0
+ >;
+ clock-output-names =
+ "intca0";
+ };
};
};