summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/sh73a0.dtsi
diff options
context:
space:
mode:
authorSimon Horman <horms+renesas@verge.net.au>2012-11-21 16:12:43 +0400
committerSimon Horman <horms+renesas@verge.net.au>2013-01-25 07:43:48 +0400
commita3f22db5102238197d5f6bbcad2f720ec7f09e10 (patch)
treefbe330c446e6d05b7f681a0f3d87dbeba09cc7ac /arch/arm/boot/dts/sh73a0.dtsi
parent20aa11358d52e1a3fc037d601ffe704e6f55c5fb (diff)
downloadlinux-a3f22db5102238197d5f6bbcad2f720ec7f09e10.tar.xz
ARM: mach-shmobile: sh73a0: Allow initialisation of GIC by DT
This allows the GIC interrupt controller of the sh73a0 SoC to be initialised using a flattened device tree blob. It does not allow the INTC interrupt controller which is also present on the sh73a0 SoC to be enabled via device tree. Nor does it handle sharing of interrupts between the GIC and INTC interrupt controllers. This limits the usefulness of this code to applications which only wish to access devices which use interrupts that can be handled by the GIC interrupt controller. Other applications should, for now, continue using non-device tree initialisation of the sh72a0 interrupt controllers. Includes update to use irqchip_init() by Thierry Reding Cc: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/sh73a0.dtsi')
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi33
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
new file mode 100644
index 000000000000..7dae1f4e9be3
--- /dev/null
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -0,0 +1,33 @@
+/*
+ * Device Tree Source for the SH73A0 SoC
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "renesas,sh73a0";
+
+ cpus {
+ cpu@0 {
+ compatible = "arm,cortex-a9";
+ };
+ cpu@1 {
+ compatible = "arm,cortex-a9";
+ };
+ };
+
+ gic: interrupt-controller@f0001000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ interrupt-controller;
+ reg = <0xf0001000 0x1000>,
+ <0xf0000100 0x100>;
+ };
+};