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| author | Dinh Nguyen <dinguyen@kernel.org> | 2022-10-03 21:26:50 +0300 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2022-11-18 20:13:49 +0300 |
| commit | 3b500ff37ce3ef5d7fbb731d082ef8f4cddce0f1 (patch) | |
| tree | d71c942c03f064862d41b4867041a98d1e30a3cb /arch/arm/boot/dts/socfpga_arria10.dtsi | |
| parent | 63fb606a59a4e51572b2f34589b4afd00536f185 (diff) | |
| download | linux-3b500ff37ce3ef5d7fbb731d082ef8f4cddce0f1.tar.xz | |
arm: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node
The sdmmc controller's CIU(Card Interface Unit) clock's phase can be
adjusted through the register in the system manager. Add the binding
"altr,sysmgr-syscon" to the SDMMC node for the driver to access the
system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to
designate the smpsel and drvsel properties for the CIU clock.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/socfpga_arria10.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/socfpga_arria10.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index cc7d4a62dde7..3b2a2c9c6547 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -665,6 +665,7 @@ clocks = <&l4_mp_clk>, <&sdmmc_clk>; clock-names = "biu", "ciu"; resets = <&rst SDMMC_RESET>; + altr,sysmgr-syscon = <&sysmgr 0x28 4>; status = "disabled"; }; |