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| author | Stephan Gerhold <stephan@gerhold.net> | 2019-11-25 15:22:55 +0300 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2019-12-09 16:45:01 +0300 |
| commit | 99e1df6136254c2b763d3d5ad23ede005f2e5b2b (patch) | |
| tree | 1aa1de77525d6b0de3e66f1c14432c6b4e357b29 /arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi | |
| parent | 4dbeac7364647c91be0591d504d149b6ddd1da90 (diff) | |
| download | linux-99e1df6136254c2b763d3d5ad23ede005f2e5b2b.tar.xz | |
ARM: dts: ux500: Add pin configs for UART1 CTS/RTS pins
UART1 can optionally be used with additional CTS/RTS pins.
The pinctrl driver has an extra "u1ctsrts_a_1" pin group for them.
Add a new pin configuration to configure them correctly if needed.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191125122256.53482-4-stephan@gerhold.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi b/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi index b6d0a60e9aed..e85a08ad2ea7 100644 --- a/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0-pinctrl.dtsi @@ -65,6 +65,32 @@ ste,config = <&slpm_out_wkup_pdis>; }; }; + + u1ctsrts_a_1_default: u1ctsrts_a_1_default { + default_mux { + function = "u1"; + groups = "u1ctsrts_a_1"; + }; + default_cfg1 { + pins = "GPIO6_AF6"; /* CTS */ + ste,config = <&in_pu>; + }; + default_cfg2 { + pins = "GPIO7_AG5"; /* RTS */ + ste,config = <&out_hi>; + }; + }; + + u1ctsrts_a_1_sleep: u1ctsrts_a_1_sleep { + sleep_cfg1 { + pins = "GPIO6_AF6"; /* CTS */ + ste,config = <&slpm_in_wkup_pdis>; + }; + sleep_cfg2 { + pins = "GPIO7_AG5"; /* RTS */ + ste,config = <&slpm_out_hi_wkup_pdis>; + }; + }; }; uart2 { |