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authorLudovic Barre <ludovic.barre@st.com>2018-04-30 10:11:00 +0300
committerAlexandre Torgue <alexandre.torgue@st.com>2018-05-04 10:45:49 +0300
commit8440300573392cdd2653a3f6072f855684998421 (patch)
treeb00f70538985191783090bda8298958334b5f606 /arch/arm/boot/dts/stm32mp157c-ev1.dts
parentc38928d638f16611ea0534374d212b205976c37a (diff)
downloadlinux-8440300573392cdd2653a3f6072f855684998421.tar.xz
ARM: dts: stm32: add flash nor support on stm32mp157c eval board
This patch adds flash nor on qspi. Each flash is connected in quad mode and has its own chip select. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Diffstat (limited to 'arch/arm/boot/dts/stm32mp157c-ev1.dts')
-rw-r--r--arch/arm/boot/dts/stm32mp157c-ev1.dts25
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts
index fa3df6bf8a55..9382d8063031 100644
--- a/arch/arm/boot/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts
@@ -42,6 +42,31 @@
status = "okay";
};
+&qspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
+ reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash0: mx66l51235l@0 {
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ flash1: mx66l51235l@1 {
+ reg = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
&timers2 {
status = "disabled";
pwm {