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authorMaxime Ripard <maxime.ripard@bootlin.com>2019-03-25 16:52:48 +0300
committerMaxime Ripard <maxime.ripard@bootlin.com>2019-03-25 23:28:16 +0300
commit1b97cf4987fb2e3242880d460a530eaccd8c4759 (patch)
treefad20661df1e677b60bf93cb42726266d4180c81 /arch/arm/boot/dts/sun8i-a23-a33.dtsi
parent1befb26623737d77f5ed43d5e24a28a7f666088d (diff)
downloadlinux-1b97cf4987fb2e3242880d460a530eaccd8c4759.tar.xz
ARM: dts: sun8i: A23/A33: Fix pinctrl node names
The NAND pinctrl nodes names don't follow the pattern we've used and enforced for some time. Make sure they do. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'arch/arm/boot/dts/sun8i-a23-a33.dtsi')
-rw-r--r--arch/arm/boot/dts/sun8i-a23-a33.dtsi10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 9be25db7a275..6d43e06d8cc5 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -170,7 +170,7 @@
resets = <&ccu RST_BUS_NAND>;
reset-names = "ahb";
pinctrl-names = "default";
- pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>;
+ pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -394,25 +394,25 @@
function = "nand0";
};
- nand_pins_cs0: nand-pins-cs0 {
+ nand_cs0_pin: nand-cs0-pin {
pins = "PC4";
function = "nand0";
bias-pull-up;
};
- nand_pins_cs1: nand-pins-cs1 {
+ nand_cs1_pin: nand-cs1-pin {
pins = "PC3";
function = "nand0";
bias-pull-up;
};
- nand_pins_rb0: nand-pins-rb0 {
+ nand_rb0_pin: nand-rb0-pin {
pins = "PC6";
function = "nand0";
bias-pull-up;
};
- nand_pins_rb1: nand-pins-rb1 {
+ nand_rb1_pin: nand-rb1-pin {
pins = "PC7";
function = "nand0";
bias-pull-up;